cx28500 Mindspeed Technologies, cx28500 Datasheet - Page 117

• Manufacturer Part Number: cx28500
• Description: Cx28500 Multichannel Synchronous Communications Controller
• Manufacturer: Mindspeed Technologies

The Host can issue a Service Request to change the value of this register only when the affected channel is
inactive. Additionally, internal data buffer allocation must conform to the following criteria:
1. Host must set the buffers so there is no overlap between buffers belonging to different channels.
2. Allocated memory segments should not have wraparounds. That is, ending addresses must be greater than
3. The Host cannot allocate all of the FIFO to one channel. The maximal allocation to one channel is (all FIFO) –
Each transmit channel must be allocated buffer space before the channel can be activated. Other important
considerations for allocation of internal data buffers include the channel’s data rate and PCI latency tolerance. This
architecture of configured buffer allocation is completely flexible and allows the Host to assign larger FIFO buffers
to channels that operate at higher rates. For applications operating high-speed channels (i.e., hyperchanneling) the
Host can increase the FIFO allocation per channel. PCI latency tolerance equals the maximum length of time a
particular channel can operate normally between PCI bus transactions without reaching an internal overflow or
underflow condition. PCI latency tolerance is primarily dependent on each channel FIFO’s buffer size.
Table 6-32
registers, one for each channel.
Table 6-32.
6.7.4
This register, defined in
registers, one for each channel.
Table 6-33.
28500-DSH-002-C
31:29
28:16
15:13
12:0
31:17
16
GENERAL NOTE:
1. One channel maximum must be 32 KB-1 quad-words (i.e., ENDAD = 1FFEh and STARTAD = 0000h).
2. ENDAD must be greater than STARTAD (i.e., no rollover).
3. Minimal allocation to any channel ≥ 4 dwords (i.e., ENDAD – STARTAD ≥ 3).
FOOTNOTE:
(1)
(2)
Bit
TDMA_ENDAD must be an odd address (i.e., LSB must be 1).
TDMA_STARTAD must be an even address (i.e., LSB must be 0).
data than the threshold, no transfer is generated unless there is already an EOM, meaning a whole message,
in the internal FIFO.
starting addresses.
1 quad dwords.
Bit
describes the bit fields in TDMA Buffer Allocation register. There are 1024 TDMA Buffer Allocation
TDMA Buffer Allocation Register
TDMA Channel Configuration Register (1 of 2)
TDMA_STARTAD[12:0]
TDMA_ENDAD[12:0]
Field Name
EOCEIEN
TDMA Configuration Register
RSVD
Field Name
RSVD
RSVD
Table
6-33, controls per channel the TxDMA operational mode. There are 1024 such
(1)
(2)
Value
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0
0
1
Value
—
—
Reserved.
End Of Command Execution Interrupt disabled.
End Of Command Execution Interrupt enabled. Interrupt generated when a command
(Activate, Deactivate or Jump) execution was completed.
0
0
Reserved.
Ending address of internal channel data buffer.
Reserved.
Starting address of internal channel data buffer.
®
Description
Description
Memory Organization
102