ibm3206k0424 ETC-unknow, ibm3206k0424 Datasheet - Page 62

• Manufacturer Part Number: ibm3206k0424
• Description: Ibm Processor For Network Resources
• Manufacturer: ETC-unknow

IBM3206K0424
IBM Processor for Network Resources
Receive Packet Definitions
The minimum receive packet offset is 0xC bytes. When the optional fields are enabled, the receive packet off-
set increases and should be set appropriately in the receive LCD. See RXAAL Packet Header Configuration
on page 352 for available word choices and definitions.
Transmit and Receive Packet Header Field Descriptions
Packet Header
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AAL5_user_byte1
generate_CRC10
queue_on_xmit
dma_on_xmit
free_on_xmit
Field Name
next_buffer
If this bit is set, CRC10 will be generated over the cell(s) in this packet.
If this bit is set, the buffer will be queued on the transmit complete queue after the transmission completes.
This field is used by the hardware to chain buffers together on queues. It contains the address of the next
buffer if one exists. For transmit buffers allocated in virtual memory, this field is written by the hardware with a
distinctive pattern (’zzzzzBAD’x) where zzzzz is the offset of the failure when a write operation was not able to
complete due to a shortage of the real buffers needed to map into the virtual address space. This field can be
checked after all buffer write operations and the appropriate recovery actions are taken immediately, or when
a buffer that has had a write failure is enqueued to CSKED (an event will be generated and the buffer will not
be processed by CSKED). A status bit also exists in the BCACH status register indicating that a write to virtual
memory has failed. With cache performance in mind, this status bit could be checked first; if it is not set, there
is no need to access the header of the packet.
Note: This automatic error recovery mechanism results in the restriction that this first four bytes of a transmit
packet must never be written via programmed IO or DMA during preparation for transmission. If this field is
written by a software or DMA operation, the automatic error detection will not work properly and undesirable
results are likely.
On transmit, this field contains the value to be sent in the user byte in the last cell of an AAL5 packet, if INTST
is configured for one user byte.
On receive, this field contains the user byte from the AAL5 trailer, if INTST is configured for one user byte.
When not configured for AAL5, this field is redefined. The two most significant bits contain the drop number.
When in packet mode, the low five bits of this byte contain the number of bytes dropped due to the dropN-
Bytes field in the LCD.
If this bit is set, a DMA descriptor address placed in the packet header (offset 0xC) will be queued for execu-
tion.
If this bit is set, the buffer will be freed after the transmission completes.
Field Description
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pnr25.chapt03.01
August 14, 2000
Preliminary