ibm3206k0424 ETC-unknow, ibm3206k0424 Datasheet - Page 193

• Manufacturer Part Number: ibm3206k0424
• Description: Ibm Processor For Network Resources
• Manufacturer: ETC-unknow

Preliminary
pnr25.chapt04.01
August 14, 2000
15-12
Bit(s)
11-8
7-6
5
4
3
2
1
0
T
T
Reserved
POR
Self Refresh
Initialize SDRAMs
Start Power on Reset Sequence
Enter the Self Refresh State
Exit the Self Refresh State
RP
RC
Delay
Delay
Function
The value of these four bits determines the number of cycles after a bank precharge
starts before the bank may be accessed again. To determine the value needed in
these bits, take the T
be used, divide by 7.5 ns, and round up if necessary. If Tdpl is 2, Trp may need to be
increased by one to insure correct operation. Suggested values are:
X’4’
X’2’
X’2’
The value of these four bits determine the bank cycle time. To determine the value
needed in these bits, take the T
the part to be used, divide by 7.5 ns, and round up if necessary. Suggested values
are:
X’A’
X’5’
X’5’
Reserved
When set to ’1’, this bit indicates the POR sequence has not been performed on the
SDRAMs. This bit automatically resets to ’0’ when the POR sequence has been per-
formed.
This bit reads ’1’ when the SDRAMs are in the self refresh state. This bit reads ’0’
when the SDRAMs are not in the self refresh state. This bit is ’1’ after a POR or reset.
The exit self refresh operation must be performed before the POR sequence is initi-
ated.
This bit effectively encapsulates the functions provided by bits 2 and 0. Setting this bit
to ’1’ causes the memory controller to take the SDRAMs out of self refresh and per-
form the POR sequence on them. This bit clears itself. When the initialization is com-
plete, bits 4 and 5 should be a ’0’.
When set to ’1’, this bit causes the DRAM controller to initiate the SDRAM power on
sequence. This includes an all-banks precharge, following by a command register
write that sets the CAS latency to 3, the wrap type to sequential, and the burst length
to 1, followed by two refresh cycles. After this sequence is initiated and completed, bit
5 resets and the SDRAMs are ready for normal use.
When set to ’1’, this bit causes the SDRAM controller to signal the SDRAMs to go into
the self refresh state. All memory activity is suspended. Once the SDRAMs have
entered the self refresh state, bit 4 will set. This bit will clear itself.
When set to ’1’, this bit causes the SDRAM controller to signal the SDRAMs to exit the
self refresh state. Once the SDRAMs have exited the self refresh state, bit 4 will clear.
This bit will clear itself.
6.8 ns SDRAM
6 ns ESDRAM
7.5 ns ESDRAM
6.8 ns SDRAM
6 ns ESDRAM
7.5 ns ESDRAM
RP
parameter from the specification of the SDRAM of the part to
RC
parameter from the specification of the SDRAM of
Description
IBM Processor for Network Resources
The DRAM Controllers (COMET/PAKIT)
Page 193 of 676
IBM3206K0424