ibm3206k0424 ETC-unknow, ibm3206k0424 Datasheet - Page 142

• Manufacturer Part Number: ibm3206k0424
• Description: Ibm Processor For Network Resources
• Manufacturer: ETC-unknow

IBM3206K0424
IBM Processor for Network Resources
2.8: INTST CPB Status
This register holds the status bits for errors on the Control Processor bus. These bits, when disabled, will set
a bit in the INTST Interrupt Source register. See Note on Set/Clear Type Registers on page 93 for more
details on addressing.
Length
Type
Address
Restrictions
Power on Reset value
Interrupt and Status/Control (INTST)
Page 142 of 676
23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
23-20
Bit(s)
19
18
17
16
15
14
13
12
Internal DMA Masters signaled
error indication
Power Mgmt State Change
Target Abort: Register Access
Retry Timeout
Target Abort: Slave Access Tim-
eout
PCI timing changed
ARBIT Detected Memory Errors
Reserved
Reserved
Master PCI Parity Error
Detected
Function
24 bits
Clear/Set
XXXX 0430 and 34
None
X’00000’
The PCINT entity will set these bits when it signals a DMA error indication to one of the
internal requesting masters. Bit 23 is GPDMA, bit 22 is PCORE, bit 21 is RXQUE, and bit
20 is INTST.
This bit is set when the conditions in PCINT are met to trigger a Power Management State
change.
This bit is set when this slave does more retry cycles than the specified amount in the
PCINT Count Timeout Register during a register access.
This bit is set when this slave does not access the IBM3206K0424 in the specified amount
in the PCINT Count Timeout Register.
The PCI bus clock has changed range. The IBM3206K0424 should be reset and re-initial-
ized.
This bit is set when error conditions detected by ARBIT are enabled. Note: This bit is a
reflection of the arbitrator status bits and does not need to be reset if the arbitrator condi-
tion has been reset.
Reserved
Reserved
This bit is set when a PCI bus data parity error is detected in master mode.
8
7
6
5
4
Description
3
2
1
0
pnr25.chapt04.01
August 14, 2000
Preliminary