ibm3206k0424 ETC-unknow, ibm3206k0424 Datasheet - Page 208

• Manufacturer Part Number: ibm3206k0424
• Description: Ibm Processor For Network Resources
• Manufacturer: ETC-unknow

IBM3206K0424
IBM Processor for Network Resources
ATM Virtual Memory Logic (VIMEM)
Page 208 of 676
Bit(s)
11
10
9
8
7
6
5
4
3
2
1
0
When set, this bit indicates that the Virtual Memory logic has detected a non-recoverable page fault error when attempting to
write memory. This indicates that no real buffer was available to map into the virtual address space when required. All virtual
writes that fail during a page fault, with the exception of BCACH and RAALL operations, cause this bit to be set.
When set, this bit indicates that the Virtual Memory logic has detected a recoverable page fault error when attempting to
write memory. This indicates that no real buffer was available to map into the virtual address space when required. Opera-
tions from BCACH and RAALL cause this bit to be set instead of the non-recoverable bit because the software can recover
from these failures. If a BCACH write to Virtual Memory fails in this manner, the packet header of the frame being updated is
updated to indicate the failure. Software can check the field in the packet header to ensure that the DMA operation com-
pleted successfully. If such a packet is enqueued to CSKED, the packet header is checked and will prevent the frame from
being passed on to the segmentation logic. When CSKED encounters a frame that has had this type of failure, there are sev-
eral possible ways in which it can be configured (via the CSKED control register) to handle the situation. It can be configured
to ignore the error and attempt to transmit the frame anyway (probably not a good way), or the buffer can be freed back to
POOLs, or an event can be generated to allow the software to deal with the situation. If a RAALL write to Virtual Memory fails
in this manner, the packet currently being received is dropped; it is up to the software to perform any recovery operations that
are required.
When set, this bit indicates that the Virtual Memory logic has detected a read operation that caused a page fault. This is an
invalid condition because the data required for a read operation should have been previously initialized by a write operation,
so no page fault should ever occur on a read operation. If the corresponding bit in the lock register is reset, a page is mapped
into the current virtual buffer segment and the data that previously was written in that page is returned. This bit can come on
in several situations that are not really errors. In these cases, the associated interrupt and lock bits can be reset so that this
error does not cause the adapter to halt normal operation. Several of these conditions are: When predictive fill is enabled, a
read from the end of a buffer may cause a predictive read that crosses a virtual segment boundary and causes this bit to be
set. If a small buffer (fits entirely in the cache) is copied from one IBM3206K0424 buffer to another IBM3206K0424 buffer, a
subsequent read of the last bytes written causes this bit to be set if the cache hasn’t been flushed between the write and the
read, and the last write cycle did not write all four bytes, and the address that is being written/read is within the first 0x20
bytes of a virtual segment.
When set, this bit indicates that the Virtual Memory logic has detected an access of a virtual buffer that falls above the limit
set by the buffer maximum size register.
When set, this bit indicates that the Virtual Memory logic has detected an access that does not fall in one of the currently
mapped buffer segments based upon the currently-configured virtual buffer map size.
When set, this bit indicates that a virtual access has been detected that used a base register that had an invalid associated
buffer size configured in the low order bits.
When set, this bit indicates that a virtual access has been detected that used a base register that was not on the correct
memory boundary. For example, if a base register is set up to use 2K buffers, then the base register must be set up on a 2K
boundary.
When set, this bit indicates that a virtual access has been detected that used a base register that contained a value of ’0’.
Reserved.
When set, this bit indicates that the Virtual Memory logic has detected a memory access that resulted in the generation of a
buffer index that was greater than the currently configured maximum derived from the VIMEM Virtual Memory total bytes reg-
ister.
When set, this bit indicates that the currently configured size of buffers is invalid.
When set, this bit indicates that the map base register contains an invalid value. Two possible causes are that bits 5-2 are
not ’0’ or bits 31-6 are ‘0’.
Description
pnr25.chapt04.01
August 14, 2000
Preliminary