ibm3206k0424 ETC-unknow, ibm3206k0424 Datasheet - Page 124

• Manufacturer Part Number: ibm3206k0424
• Description: Ibm Processor For Network Resources
• Manufacturer: ETC-unknow

IBM3206K0424
IBM Processor for Network Resources
The IOP Bus Specific Interface Controller (PCINT)
Page 124 of 676
25-24
23-16
Bit(s)
15-8
7
6
5
4
3
2
1
0
Reserved
Arbitration priority
VsHurryUp
RqHurryUp
PrHurryUp
Rd8Bytes
Unused
4Byte32
A32SwapWords
Assume32
Encoded Control for DMA reads
Name
Encoding of bits:
X’0’: Let the IBM3206K0424 pick the best memory read command based on the cacheline
size bits and the DMA count.
X’1’: Fix the read DMA command to Memory Read Multiple.
X’2’: Fix the read DMA command to Memory Read Line.
X’3’: Fix the read DMA command to Memory Read.
Reserved
PCI master will cease using a default round-robin scheme for internal requestor arbitration
if these bits are not all ’0’. Bits 15-14 are the priority level for GPDMA. Bits 13-12 are the
priority level for PCORE. Bits 11-10 are the priority level for RXQUE. Bits 9 - 8 are the pri-
ority level for INTST. Valid levels are 3,2,1, and 0. Only 4 levels must be used.
PCI master will inform GPDMA to HurryUp if VSTAT is waiting.
PCI master will inform GPDMA to HurryUp if RXQUE is waiting.
PCI master will inform GPDMA to HurryUp if PCORE is waiting.
PCI master will force all byte enables active for reads.
PCI master does not use this bit.
PCI master will transfer a four-byte DMA as a 32-bit transfer.
PCI master will always swap words for any Assume32 transfer.
PCI master will not request a 64-bit transfer.
Description
pnr25.chapt04.01
August 14, 2000
Preliminary