ibm3206k0424 ETC-unknow, ibm3206k0424 Datasheet - Page 111

• Manufacturer Part Number: ibm3206k0424
• Description: Ibm Processor For Network Resources
• Manufacturer: ETC-unknow

Preliminary
1.14: PCINT Base Address Control Register
This register controls all the base address registers that map to memory. See bit definitions.
Length
Type
Address
Restrictions
Power on Reset value
(Big Endian)
Power on Reset value
(Little Endian)
pnr25.chapt04.01
August 14, 2000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
31-24
Bit(s)
23
22
21
Reserved
Reserved
Allow decoding for zero Base
Address values
Enforce sequential PCI register
writes
Enforce sequential PCI register
reads
Function
32 bits
Read/Write
XXXX 005C
Can be written or read during configuration cycle, memory cycle when enabled (see
PCINT Base Address Control Register on page 111), or an I/O cycle. This register
is documented as big endian, but how data is presented on the PCI bus depends
on how the controls are set in the PCINT Endian Control Register.
X’0001000F’
X’0F001100’
Reserved
Setting this bit to ’1’ will enables decoding of a BAR address that is set to ’0’. Normally,
the PCI specification does not allow for a zero address to be a valid decode.
Setting this bit to ’1’ ensures that PCI register writes will occur in sequential order of
prior memory accesses or register reads. The cost for doing this is possible extra retry
cycles for accesses not dependent on other posted accesses to complete.
Setting this bit to ’1’ ensures that PCI register reads will occur in sequential order of
prior memory accesses or register writes. The cost for doing this is possible extra retry
cycles for accesses not dependent on other posted accesses to complete.
The IOP Bus Specific Interface Controller (PCINT)
Description
IBM Processor for Network Resources
9
8
7
6
5
4
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