ibm3206k0424 ETC-unknow, ibm3206k0424 Datasheet - Page 246

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ibm3206k0424

Manufacturer Part Number
ibm3206k0424
Description
Ibm Processor For Network Resources
Manufacturer
ETC-unknow
Datasheet
IBM3206K0424
IBM Processor for Network Resources
8.8: BCACH Cache Line Array
This array is divided into four 32-byte buffers used as cache lines 0, 1, 2, and 3.
Length
Type
Address
Restrictions
The Bus DRAM Cache Controller (BCACH)
Page 246 of 676
Bit(s)
Bit(s)
3-0
??
Dirty bits
The four cache lines start at the following offsets into the array:
Line 0
Line 1
Line 2
Line 3
Function
Offset X'00'
Offset X'20'
Offset X'40'
Offset X'60'
16 Words x 64 bits
Read/Write
XXXX 1100 - 17F
This array can only be accessed when the diagnostic mode bit in the control regis-
ter is set.
These bits, when set, indicate that the associated eight-byte word of the cache line is dirty.
This information is used on cache line flushes, to lower memory utilization, by eliminating
non-dirty word flushes from the cache line flush operation. For example if these bits contain
a X’1’, only the eight-byte word at offset zero in the cache line is dirty, so the flush operation
will only write this one word to memory, saving three memory access cycles. If these bits
contain a X’C’, only the two eight-byte words starting at offset X’10’ in the cache line are
dirty.
Description
Description
pnr25.chapt04.01
August 14, 2000
Preliminary

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