ibm3206k0424 ETC-unknow, ibm3206k0424 Datasheet - Page 457

• Manufacturer Part Number: ibm3206k0424
• Description: Ibm Processor For Network Resources
• Manufacturer: ETC-unknow

Preliminary
pnr25.chapt05.01
August 14, 2000
23-18
Bit(s)
10-1
26
25
24
17
16
15
14
13
12
11
0
IP/EVPR Override
Debug Mode Select
WE Enable
Reserved
Data Cache Enable
Instruction Cache Enable
Disable Instruction/CR-logical-op
Pairing
Disable Instruction/Branch Pairing 1 = disable, 0 = enable
Disable Conditional Dispatch
Disable Instruction Pipelining
Allow Data Machine Checks to be
Imprecise
Reserved
Enable Checkstop on Machine
Check
Name
When ’1’, EVPR contents are used as the upper 16 bits of the exception vector,
regardless of the value of MSR(IP). When ’0’, MSR(IP) determines the upper 16 bits of
the exception vector.
Note: eeee = EVPR register contents, vvvv = exception vector offset (for example,
0700)
A ’0’ enables the BE and SE bits of the MSR to function as a 60x, a ’1’ enables the
MSR(DE) bit as a 40x.
Note: All 40x debug facilities (IAC, DAC, etc.) are disabled when in 60x mode.
Enables the MSR(WE) bit to cause a 40x style WE. 0 = disabled, 1 = enabled
Reserved
0 = disable, 1 = enable
1 = disable, 0 = enable
1 = disable, 0 = enable
Setting this to ’1’ will result in a very small performance gain, at the expense of accu-
racy in the SRR0/2 of a machine check.
Reserved
When ’1’, a machine check which occurs when MSR(ME)=0 will cause the hardware to
freeze, maintaining much of the state of the machine. When ’0’, the processor will
attempt to continue execution when a machine check occurs when MSR(ME)=0. When
MSR(ME)=1 and a machine check occurs, a machine check exception is taken regard-
less of the setting of this bit.
0 = disable, 1 = enable
1 = disable, 0 = enable
HID0(IPO=26) MSR(IP=25)
0
0
1
0
1
-
Exception Vector
0xFFF0vvvv
0x0000vvvv
0xeeeevvvv
Description
IBM Processor for Network Resources
Processor Core (PCORE)
Page 457 of 676
IBM3206K0424