ibm3206k0424 ETC-unknow, ibm3206k0424 Datasheet - Page 456

• Manufacturer Part Number: ibm3206k0424
• Description: Ibm Processor For Network Resources
• Manufacturer: ETC-unknow

IBM3206K0424
IBM Processor for Network Resources
17.1: Hardware Implementation Detail 0 Register (HID0)
Enables caches and controls architecture specific functionality. This register controls whether Cobra Core
acts as a 40x or 60x series processor and allows the different features of each architecture to be individually
selected.
Length
Type
Address
Power on Reset value
Restrictions
Processor Core (PCORE)
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31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Bit(s)
31
30
29
28
27
No-Op Touch Instructions
Reserved
Disable decrementer
Disable alignment interrupts on
lmw/stmw
SRR1/3 Style
Name
32 bits
Read/Write
1023
X’00 00 00 FC’ (40x mode)
X’80 00 00 00’ - Alternative value (60x mode suggested value)
Reserved
0 = touch instructions work; 1 = touch instructions disabled
Reserved
When ’0’, the decrementer register is a free running countdown register which causes
a decrementer interrupt when it decrements through ’0’. When ‘1’, the decrementer
register does not decrement.
When ’0’, lmw/stmw instructions to non-word aligned addresses cause alignment inter-
rupts (60x mode). When ’1’, lmw/stmw instructions never cause alignment interrupts
(40x mode).
When ’0’, interrupts cause srr1/3 to receive interrupt codes in bits 0:15, and MSR con-
tents in bits 16:31. Likewise, rfi/rfci restore bits 16:31 of srr1/3 to the MSR. When ’1’,
interrupts cause srr1/3 to receive MSR contents in bits 0:31. Likewise, rfi/rfci restore
bits 0:31 of srr1/3 to the MSR. Status is stored in ESR register regardless.
Description
9
8
7
Reserved
6
5
4
pnr25.chapt05.01
August 14, 2000
3
Preliminary
2
1
0