ibm3206k0424 ETC-unknow, ibm3206k0424 Datasheet - Page 135

• Manufacturer Part Number: ibm3206k0424
• Description: Ibm Processor For Network Resources
• Manufacturer: ETC-unknow

Preliminary
Entity 2: Interrupt and Status/Control (INTST)
This entity contains the masking registers that choose which interrupt/status source will be gated onto one of
the two available interrupt I/O pins. A new delayed interrupt function has been added. This function allows
IBM3206K0424 status registers to be read and placed in system memory before the interrupt signal is raised.
For details, see DMA QUEUES (DMAQS) on page 154.
A bus timer function is provided in this entity that times a single bus access to make sure that the cycle is ter-
minated before the system timer times out. This allows the user code an opportunity to recover from the error
as opposed to the subsystem common code.
Below is a summary of this entity’s functions:
2.1: INTST Interrupt 1 Prioritized Status
Used to help quickly parse which interrupting entity of the IBM3206K0424 is active.
Length
Type
Address
Restrictions
Power on Reset value
pnr25.chapt04.01
August 14, 2000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
• Interrupt Prioritized Status Registers
• Interrupt Source Register
• Interrupt Enable Registers
• Bus timer function
• Control Processor error register with enable register
Bit(s)
31-0
Prioritized Status
Function
32 bits
Read Only
XXXX 0400
None
X’00000000’
Reading this register will give a prioritized value of the bits in the INTST Interrupt Source
and INTST Enable for Interrupt 1 (MINTA) registers ANDed together, returning a value that
will be a hex number equal to bit number n + 1. For example, if bit 31 is on, X’20’ will be
read back.
Prioritized Status
Description
IBM Processor for Network Resources
8
Interrupt and Status/Control (INTST)
7
6
5
4
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