ibm3206k0424 ETC-unknow, ibm3206k0424 Datasheet - Page 417

• Manufacturer Part Number: ibm3206k0424
• Description: Ibm Processor For Network Resources
• Manufacturer: ETC-unknow

Preliminary
pnr25.chapt05.01
August 14, 2000
26-19
21-20
18-16
15-13
Bit(s)
19
18
17
16
12
11
10
Reserved
Modify byte alignment in 16-bit
PHY mode
These bits only have meaning if a PMC PM5346 SUNI LITE/UTOPIA (bits 31-29 = "011") is selected. If any other device is
chosen these bits will be ignored.
52 Byte Cell
Disable HEC Generation on
Transmitted Cells
Parity on all 16 bits
PHY Receive Device
Enable Parity Checking
Even/Odd Parity Selection
PHY Data Path Size
Name
Reserved
The value of bits 21-20 indicate the number of additional header bytes that will be read
from SEGBUF and added to the beginning of each cell as each is transmitted to the
PHY. The bytes are meant to be used for additional routing information. These control
bits have no affect in IBM 25 Mb/s PHY mode, and should be set to ’0’s when in inter-
nal SONET/SDH framer mode. If used in conjunction with 52-byte mode, the byte nor-
mally containing the cell HEC will not be transmitted and the total number of cells
transmitted will be the value of this field plus 52. If 16-bit PHY mode is selected, by
default, the byte alignment will follow that of normal 52- or 53-byte 16-bit mode, with
the additional header bytes contiguously prepended. As a result, a mode with three
additional header bytes cannot be obtained in 53-byte, 16-bit mode (LSB is normally
padded with zeros so MSB gets truncated). Bit 3 of this register is therefore provided to
adjust the alignment in 16-bit, 53-byte mode so all five header bytes will be transmitted
with up to three additional router bytes prepended.
When set to ’1’, this bit changes the default byte alignment in 16-bit PHY mode if this
register also contains a non-zero value in bits 21-20. See the description of those bits
for further details.
When set, the cell sent to the PHY is 52 bytes. No HEC byte will be sent.
If bit 17 is set to ’1’, X'00' will be placed in the HEC byte of Utopia cells. If bit 17 is set
to ’0’, the value of LINKC Transmitted HEC Control byte will be sent. If bit 18 is set to
’1’, no HEC is sent and this bit will be ignored.
When set, this bit enables the IBM3206K0424 to produce a single parity bit across the
16-bit transmit data bus. When set, the IBM3206K0424 produces two parity bits, one
across generation and the lower half of the 16 bits (parity bit 0) and one against the
upper (parity bit 1). The default for this bit is ’1’.
Bits 15, 14, and 13 indicate to which PHY the IBM3206K0424's Receive Config 3 will
be interfacing. If the configuration's port address is all ones, then the configuration is
unused and the value above bits doesn't matter.
'000'
'001'
'010'
'011'
'100'
'101'
'111'
When set, this bit enables checking of parity on data from the receive path. The default
parity checking is disabled. The upper bit of the transmit parity is not valid when the
internal SONET/SDH Framer has been selected as the receive PHY device. The upper
bit of the receive parity is also not valid when the internal SONET/SDH Framer has
been selected as the transmit PHY device. This is only a concern if a combination of
the internal framer and an external PHY is being used and that external PHY has a
16-bit data interface. In this case, parity cannot be checked/generated on the upper
byte.
Even parity is selected when this bit is cleared. The default value is for odd parity.
This bit, when set to ’0’, selects a 16-bit wide data path to the PHY device. When set to
’1’, the data path width to the PHY will be eight bits. This bit has no affect on the inter-
nal SONET/SDH framer except if the internal framer has been selected as the Rx PHY
device but not as the Tx PHY device. In this case, a ’1’ on this bit will allow FYT-
DAT(15-13) to be used for the 16-bit external Tx PHY device, while a zero will allow
FYTDAT(15-13) to be used for the Rx HDLC controller. This implies that it is not possi-
ble to use the internal RX framer, the RX HDLC interface, and an external 16-bit TX
framer at the same time.
Reserved
PMC POS-PHY (Frame based Utopia)
Reserved
PMC PM5346 SUNI LITE/UTOPIA interface (STS-3c/STM-1 OR STS-1)
Reserved
Reserved
Reserved
Description
IBM Processor for Network Resources
The PHY Interface (LINKC)
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IBM3206K0424