ibm3206k0424 ETC-unknow, ibm3206k0424 Datasheet - Page 143

• Manufacturer Part Number: ibm3206k0424
• Description: Ibm Processor For Network Resources
• Manufacturer: ETC-unknow

Preliminary
pnr25.chapt04.01
August 14, 2000
Bit(s)
11
10
9
8
7
6
5
4
3
2
1
0
Master Detected Perr Active
Master Termination: Target
Abort Received
Master Termination: Master-initi-
ated Abort
Target Detected PCI 64 Bit Data
Parity Error
Target Disconnect: Memory
Addressing
Target Detected PCI Data Parity
Error
Target Abort: Memory Access
Retry Timeout
Target Abort: Address Parity
Error
Target Disconnect or Retry:
Wrap of 2 GB internal address
slave counter
Performance Counter 2
Performance Counter 1
Illegal Register Access
Function
This bit is set when a target has driven PERR.
This bit is set when in master mode and the transfer is aborted by the target.
This bit is set when in master mode and the transfer is aborted by this master.
This bit is set when a PCI data parity error is detected in 64 bit target mode (the upper
DWORD has the data parity error).
This is set when a memory access is occurring and bits 0 and 1 of the address are not ’0’.
This bit is set when a PCI data parity error is detected in target mode.
This bit is set when this slave does more retry cycles than the specified amount in the
PCINT Count Timeout Register during a memory access.
This bit is set when an address parity error is detected.
This bit is set when the slave address counter is its maximum counter value will indicate a
termination condition on the PCI bus. This is primarily a debug bit and can turn on during
normal operation. It most likely will be useful when the IBM3206K0424 slave mode is con-
figured in 64-bit addressing mode.
The PCINT Performance Counter 2 has overflowed.
The PCINT Performance Counter 1 has overflowed.
This bit is set when an IBM3206K0424 register is being accessed by fewer than four bytes
at a time. This is not true for configuration registers during a configuration cycle.
Description
IBM Processor for Network Resources
Interrupt and Status/Control (INTST)
Page 143 of 676
IBM3206K0424