ibm3206k0424 ETC-unknow, ibm3206k0424 Datasheet - Page 526

• Manufacturer Part Number: ibm3206k0424
• Description: Ibm Processor For Network Resources
• Manufacturer: ETC-unknow

IBM3206K0424
IBM Processor for Network Resources
Preliminary
Handshaking Error Registers
Each bit of the handshaking error registers indicates a locked interface to one of the chiplet GppHandlers.
Two additional bits indicate various timeout events. To reset an individual bit of the handshaking error regis-
ter, the cause for the request must be removed and a one must be written into the bit location of the register
(R/W). Reading the register will reset the whole (eight-bit) register if the corresponding "clear-register" option
is set in the configuration register. The handshaking error indication register has a corresponding MASK
register (R/W). Every unmasked, active handshaking error bit causes activation of the pointer bit in the
GPPINT interrupt register.
Clock Monitor Status Registers
The clock monitor status register bits indicate the loss of a specific chiplet’s clock. They are set whenever a
difference between the clock test signal and the individual chiplet clock acknowledge signal occurs after one
clock monitor test period. To reset an individual bit of the clock monitor status registers, the clock of the corre-
sponding chiplet must be restored and a one must be written into the bit location of the register (R/W).
Reading one of the registers will reset the whole (eight-bit) register if the corresponding "clear-register" option
is set in the configuration register. The clock monitor status register has a corresponding MASK register
(R/W). Every unmasked, active clock monitor status bit causes activation of the pointer bit in the GPPINT
register.
Local Gppint Configuration Registers
There are registers (R/W) for the Clock Monitor Test Period, the Watchdog Timer Period and the "clear-regis-
ter" option. A read-only register provides the Vital Product Data (VPD).
Global Static Configuration Registers
These are configuration parameters that are shared by many chiplets or that are needed by chiplets that have
no GppHandler. The initial values can be modified by the microprocessor after power-on, but should not be
changed later on. All global static configuration registers are R/W.
Status Registers
These registers provide status information from chiplets that have no GppHandler and are read only.
Presently, there is only one status register for the SIM chiplet (PLL lock status).
GPPINT Architecture
pnr25.chapt06.01
Page 526 of 676
August 14, 2000