ibm3206k0424 ETC-unknow, ibm3206k0424 Datasheet - Page 158

• Manufacturer Part Number: ibm3206k0424
• Description: Ibm Processor For Network Resources
• Manufacturer: ETC-unknow

IBM3206K0424
IBM Processor for Network Resources
3.1: DMAQS Lower Bound Registers
These registers specify the lower bound of the corresponding DMA queue data structure. These registers
specify the lower bound of the corresponding DMA queue data structure. The head, tail, and length of the
DMA queue are initialized when this register is written. When the DMA queue wraps past the upper bound, it
wraps back to the value in the lower bound register, thus implementing the DMA queue as a circular buffer.
When this register is written, the corresponding DMA queue is essentially reset. This is because the head,
tail, and length of the queue are all reset.
.
Length
Type
Address
Power on Value
Restrictions
DMA QUEUES (DMAQS)
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32 bits
Read/Write
Queue 0
Queue 1
Queue 2
X’00000000’
During normal operations, these registers are read only. These registers can only
be written when the diagnostic bit has been set in the DMAQS Control Register.
The alignment should correspond to the size specified in the upper bound register.
For example, it should be 4K aligned if the upper bound specifies 4K size.
The low order nine bits are not writable and read back ’0’.
604
684
704
pnr25.chapt04.01
August 14, 2000
Preliminary