ibm3206k0424 ETC-unknow, ibm3206k0424 Datasheet - Page 168

• Manufacturer Part Number: ibm3206k0424
• Description: Ibm Processor For Network Resources
• Manufacturer: ETC-unknow

IBM3206K0424
IBM Processor for Network Resources
3.14: DMAQS Transfer Count and Flag Register
This register specifies the type and number of bytes transferred during a DMA transfer. The lower 16 bits are
a counter of the number of bytes transferred during a DMA transfer. The upper 16 bits specify the type of
transfer.
Length
Type
Address
Power on Value
Restrictions
DMA QUEUES (DMAQS)
Page 168 of 676
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Bit(s)
31
30
29
28
27
26
Register Destination is 64 bits
wide
Register Source is 64 bits wide
Clear Checksum/Hold Dest
Compute Checksum/Hold Src
Little Endian Mode
Tx on DMA Complete
32 bits
Read/Write
Queue 0
Queue 1
Queue 2
X’00000000’
None
Function
These bits must be used with bits 25 and 29 (see below).
When this bit is set, the checksum and the alignment state are cleared.
When this bit is set, a checksum will be computed over this DMA segment.
When this bit is written to ’0’, this DMA channel operates in big endian mode. When set
to ’1’, the channels operate in little endian mode. In little endian mode, both the source
and destination must be aligned on four-byte boundaries.
When set, the destination address is used as the packet address that is to be
enqueued to CSKED to be transmitted. The lower bits are set to ’0’ so the buffer base
is used for the CSKED enqueue operation.
Source Address
XXXX 644
XXXX 06C4
XXXX 0744
Specifier
Description
Byte Transfer Count
9
8
7
6
5
4
pnr25.chapt04.01
August 14, 2000
3
Preliminary
2
1
0