ibm3206k0424 ETC-unknow, ibm3206k0424 Datasheet - Page 579

• Manufacturer Part Number: ibm3206k0424
• Description: Ibm Processor For Network Resources
• Manufacturer: ETC-unknow

Preliminary
Overhead Frame Processor Architecture: Transmit Direction
OFP_Tx GPP Handler Address Mapping
pnr25.chapt06.01
August 14, 2000
1. Independent of the counter width, given that a counter has chiplet address N as a base. Reading address N or address N-1 both
2. Address range 100-17F located in 128x8 GRA. Address range 180-1BF located in 64x8 GRA.
3. The 64-byte J1 path trace processing uses the 16-byte addresses of 16 byte J1 path trace to map a full 64 byte space
Register Name
JUSCNTTh11
M_CntrIRQ1
ND_EVCNT
M_MainIRQ
yield the least significant byte of the counter. Reading address N has no affect on the counter, but reading address N-1 resets the
counter after read operation
CntrIRQ1
SOH-A11
SOH-A12
SOH-A13
SOH-A21
SOH-A22
PTRDEC
JUSCNT
MainIRQ
CONF10
PTRINC
M_IRQ3
CONF1
CONF2
CONF3
CONF4
CONF5
CONF6
CONF7
CONF8
CONF9
CntEn1
RESET
STAT1
STAT2
CMD1
IRQ3
COUNT ENABLE register
Pointer increment event counter
No threshold
Pointer decrement event counter
No threshold
New data event counter, no threshold
Justification error counter
With no threshold
Threshold register for counter JUSCNT
Default RESET register
Njus, Pjus, NDF
Init, hug, mode(7-5)
Njus, Pjus, NDF
MAIN INTerrupt register
INTerrupt MASK register (for MainIRQ)
COUNTER INTerrupt register
INTerrupt MASK register (for CntrIRQ1)
USER INTerrupt register
INTerrupt MASK register (for IRQ3)
Configuration register #1 (general A)
Configuration register #2 (general B)
Configuration register #3
(fscr reload pattern)
Configuration register #4 (errmask)
Configuration register #5 (erraddress)
Configuration register #6 (fscr control)
Configuration register #7 (DCC control)
Configuration register #8 (ThrLoW)
Configuration register #10 (ThrHiW)
First A1
Second1 A1
Third A1
First A2
Second A2
Configuration register #9 (ThrNoW)
Description
1
Base Address = x’400’ (Page 1 of 3)
1
1
1
Overhead Frame Processor Architecture: Transmit Direction
Address Offset
X’A/B’
X’4/5’
X’6/7’
X’8/9’
X’100’
X’101’
X’102’
X’103’
X’104’
X’3C’
X’3D’
X’4C’
X’4D’
X’3A’
X’3B’
X’4A’
X’4B’
X’4E’
X’4F’
X’30’
X’31’
X’33’
X’34’
X’38’
X’39’
X’48’
X’49’
X’50’
X’51’
X’2’
X’C’
IBM Processor for Network Resources
1
1
1
1
Type Width
X 4
N 8
N 8
N 8
N 8
N 8
N 8
N 8
X 8
R 2
O 3
S 6
S 3
X 3
X 5
X 6
C 8
C 3
C 8
N 8
C 8
C 8
C 8
C 4
C 6
C 6
C 6
I 3
I 5
I 6
8
8
8
8
8
Page 579 of 676
IBM3206K0424
Initial Value
’00000000’
’00000000’
’00000000’
’00000000’
’10000000’
’00000011’
’11111110’
’00000000’
’00000000’
’00000001’
’000000’
’000011’
’010001’
’100000’
’00000’
’0000’
’0000’
’000’
’000’
’000’
’01’