ibm3206k0424 ETC-unknow, ibm3206k0424 Datasheet - Page 116

• Manufacturer Part Number: ibm3206k0424
• Description: Ibm Processor For Network Resources
• Manufacturer: ETC-unknow

IBM3206K0424
IBM Processor for Network Resources
1.17: PCINT 64-bit Control Register
This register contains miscellaneous control bits.
Length
Type
Address
Restrictions
Power on Reset Value
(Big Endian)
Power on Reset Value
(Little Endian)
The IOP Bus Specific Interface Controller (PCINT)
Page 116 of 676
8
Bit(s)
7
8
7
6
5
4
3
2
6
5
Enable Master 64-bit Data path
Enable Master 64-bit Addressing
Enable Slave Register Swap Word
mode
Enable Slave 64-bit Data Path
Enable Slave 64-bit Addressing
PCI AD(63-32) Driver Control
Enable Slave Memory Swap Word
mode
4
3
2
Name
1
9 bits
Read/Write
XXXX 0078
Can be written or read during configuration cycle, memory cycle when enabled (see
PCINT Base Address Control Register on page 111), or an I/O cycle. This register
is documented as big endian, but how data is presented on the PCI bus depends
on how the controls are set in the PCINT Endian Control Register.
X’00000XXX’, where the 'X' values depend on whether bit 0 is set and values of the
enable bits in PCINT 64-bit Enable Register.
X’XX0X0000’, where the 'X' values depend on whether bit 0 is set and values of the
enable bits in PCINT 64-bit Enable Register.
0
This bit set to ‘1’ will enable master 64-bit data path for dma transfers.
This bit set to ‘1’ will enable master 64-bit addressing.
This bit set to ‘1’ will enable word swapping of the each of the four groups of data
bytes in an eight-byte register transfer. 2
This bit set to ‘1’ will enable the slave 64-bit data path for registers and Packet Mem-
ory.
This bit set to ‘1’ will enable slave 64-bit addressing, making base addresses 1 and 2
available for register accesses (memory cycles only) and base addresses 3 and 4
available for Packet Memory.
This bit set to ‘1’ will cause the AD(63-32) PCI drivers to force to tri-state unless a
64-bit access is occurring. Otherwise, when set to ‘0’, the drivers will always drive
active.
This bit set to ‘1’ will enable word swapping of the each of the four groups of data
bytes in an eight-byte slave memory transfer through BCACH. 2
Description
pnr25.chapt04.01
August 14, 2000
Preliminary