ibm3206k0424 ETC-unknow, ibm3206k0424 Datasheet - Page 297

• Manufacturer Part Number: ibm3206k0424
• Description: Ibm Processor For Network Resources
• Manufacturer: ETC-unknow

Preliminary
10.28: CSKED Interrupt Enable Register
This register is used to enable interrupts from CSKED. If a bit is on in the status register and the correspond-
ing enable bit is on in this register then an interrupt will be generated if enabled in INTST. See Note on
Set/Clear Type Registers on page 93 for more details on addressing.
Length
Type
Address
Power On Value
Restrictions
10.29: CSKED Timing Data Array Pointer
The CSKED Timing Data Array contains data relevant to scheduling cells. It contains 96 32-bit words. It
should only be written for diagnostic purposes to test the array. It will power up to all zeros and should be
rewritten to zeros after the array has been tested. This register points to an offset in the CSKED timing data
array for accesses from the PCI bus. This register must be loaded with the correct offset before the desired
data can be read from the CSKED timing data array data register. This register will auto-increment after each
access to the associated data register. When the last address is accessed, this register wraps to zero.
Length
Type
Address
Power On Value
Restrictions
pnr25.chapt05.01
August 14, 2000
13 12 11 10
8
Bit(s)
Bit(s)
13-0
Offset into CSKED
8-2
1-0
7
6
5
Enables interrupts
These bits provide an offset into the CSKED cell staging array for accesses from the PCI bus. These bits provide access
to the 256 unique four-byte locations in the array. Accessing the last location in the array will cause the address to wrap
back around to the beginning of the array.
These bits are not implemented. They cannot be written and will always return ’0’ when read.
9
4
Enables Interrupts
8
3
7
2
6
1
14 bits
Clear/Set
XXXX 1238 and 23C
X’0’
None
9 bits
Read/Write
XXXX 12C0
X’000’
None
5
0
4
3
2
1
0
Description
Description
IBM Processor for Network Resources
Debugging Register Access
Page 297 of 676
IBM3206K0424