ibm3206k0424 ETC-unknow, ibm3206k0424 Datasheet - Page 446

• Manufacturer Part Number: ibm3206k0424
• Description: Ibm Processor For Network Resources
• Manufacturer: ETC-unknow

IBM3206K0424
IBM Processor for Network Resources
Cobra Core Instruction Side
Cobra Core "Glossy" Description
The Cobra Core is a 32-bit PowerPC RISC embedded controller. It is fully compatible with the PowerPC User
Instruction Set Architecture. Details about the exact instruction set are described below. The Cobra Core has
a PowerPC instruction execution complex, separate 32k instruction and data caches, separate instruction
and data 604-style MMUs (not supported this pass), and 401-style interrupts, timers and debug facilities. The
Cobra Core has a direct connection to 96k of on-chip memory which can be used for both instruction and data
storage, as well as interfaces to the IBM3206K0424’s PCI and register buses and both of the
IBM3206K0424’s memory controllers. The DCR bus provides fastand private access to specific perfor-
mance-sensitive registers.
Features
Instruction Execution
Processor Core (PCORE)
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• Compatible with PowerPC User Instruction Set Architecture (UISA)
• Separate Branch, Condition Register, Integer, and Load/Store units for super-scalar execution
• Support for limited out-of-order execution
• Dispatches/Executes up to 2/4 instructions per clock cycle
• Four stage pipeline allowing single cycle execution for most instructions
• 32x32-bit general purpose registers (GPRs)
• Single cycle loads and stores
• Byte, halfword, word, and string accesses to any byte alignment supported in hardware
• Hardware multiply and divide (multiply up to 10 cycles, divide up to 32 cycles)
• No FPU hardware - FPU instructions result in interrupts
BPU
IMMU
ICACH
PPOCM
(I-Side)
pnr25.chapt05.01
August 14, 2000
Preliminary