ibm3206k0424 ETC-unknow, ibm3206k0424 Datasheet - Page 154

• Manufacturer Part Number: ibm3206k0424
• Description: Ibm Processor For Network Resources
• Manufacturer: ETC-unknow

IBM3206K0424
IBM Processor for Network Resources
Entity 3: DMA QUEUES (DMAQS)
DMAQS provides the interface to the IBM3206K0424’s DMA master capability (described in General Purpose
DMA (GPDMA) on page 175). It provides three DMA queues that hold DMA descriptor chains that are exe-
cuted in a multiplexed fashion. Together with GPDMA, a very powerful interface is provided to software to
complete complex tasks including TCP/IP checksumming for transmit and receive packets. The following
sections describe the features of DMAQS, how to set up DMAQS, and some troubleshooting tips.
DMA Descriptors
DMA descriptors can reside in either PCI/system memory space or the IBM3206K0424 memory space. Cer-
tain types of descriptors, called cut-through DMA descriptors, must be located in the IBM3206K0424 memory
space. DMA descriptors that are located in the IBM3206K0424 memory space are more efficient to process
because they do not need to be moved across the PCI bus. However, it is more costly for software to update
across the bus. The best option is to mix descriptors in both locations. DMA descriptors that are infrequently
changed should reside in the IBM3206K0424 memory, while dynamic descriptors should be placed in system
memory. Descriptors located in the IBM3206K0424 memory space must fall in a definable address range.
See DMAQS Local Descriptor Range Registers on page 173.
DMA QUEUES (DMAQS)
Page 154 of 676
DMA Descriptor Layout
Descriptor
One
High Order System Address
High Order System Address
Destination Address
Destination Address
Flags/Byte Count
Flags/Byte Count
Source Address
Source Address
32 bits
Blocks of up to 63 descriptors
can be queued with one
enqueue primitive.
Note: The High Order System
Address field (word 4) is not
present when the chip is in
32-bit addressing mode.
pnr25.chapt04.01
August 14, 2000
Preliminary