ibm3206k0424 ETC-unknow, ibm3206k0424 Datasheet - Page 364

• Manufacturer Part Number: ibm3206k0424
• Description: Ibm Processor For Network Resources
• Manufacturer: ETC-unknow

IBM3206K0424
IBM Processor for Network Resources
12.44: RXRTO LCD Update Op Registers
Used to specify the LCD word to update. This operation is used to update a portion of the receive LCD. If this
operation is not used, then software or the IBM3206K0424 updates of the LCD may be lost because the
receive LCD is cached in the IBM3206K0424.
This register is written with the address of the LCD word to update. Once this register is written the update
operation starts. All subsequent reads or writes to the data, mask, or update registers are held off until the
operation completes. A read-modify-write will occur to update the portion specified by the mask with the
masked value in the data register.
Normally this register would not be read. However, if it is read then the low order bit is read as ‘0’ and the next
lowest order bit (bit 1) is read as the busy bit. This signifies whether an operation is still going on. If an opera-
tion is still going on, then a new write to any of the data, mask, or update operation registers is held off until
the original operation is complete.
The second set of LCD update registers is meant for the core to use, but is available for general use.
Length
Type
Address
Power On Value
Restrictions
12.45: RXRTO RTO LCD Table Bound Registers
Used to specify the lower/upper bounds of the LCD table. The lower bound should be initialized to the LCD
index of the first LCD in the LCD table if reassembly timeout processing is to be done. The upper bound
should be initialized to the LCD index of the last LC in the LC table if reassembly timeout processing is to be
done.
Length
Type
Address
Power On Value
Restrictions
Cell/Packet Re-assembly (REASM)
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32 bits
Read/Write
Update 1 register XXXX 17C8
Update 2 register XXXX 17D8
X'00000000'
The low order two bits are not writable
16 bits
Read/Write
Lower bound 1 register
Upper bound 1 register
Lower bound 2 register
Upper bound 2 register
X'00000000'
None
XXXX 17E0
XXXX 17E4
XXXX 17F0
XXXX 17F4
pnr25.chapt05.01
August 14, 2000
Preliminary