ibm3206k0424 ETC-unknow, ibm3206k0424 Datasheet - Page 58

• Manufacturer Part Number: ibm3206k0424
• Description: Ibm Processor For Network Resources
• Manufacturer: ETC-unknow

IBM3206K0424
IBM Processor for Network Resources
Clock, Configuration, and LSSD Pin Descriptions
ATM PHY Bus Interface
Page 58 of 676
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PFFCFG (2 - 0)
MHALTPPC
JTAGnRST
MPEGCLK
JTAGTMS
JTAGTCK
Pin Name
MPCIRST
JTAGTDI
PM66EN
NSELFT
PFFOSC
PVDDA
PCICLK
TESTM
RXCLK
TXCLK
PLLTI
Input/Output
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
This signal causes a hardware reset when asserted low. See Entity 20: on page
511 for more details on resets.
The PCICLK is a 0-33, 66MHz clock.
This pin is high when on a PCI bus that runs at 33MHz - 66MHz. It is used to tell
the on-chip PLL how to generate clocks.
This is the LinkC asynchronous transmit clock.
This is the LinkC asynchronous receive clock. An oscillator should be con-
nected to RXCLK even if it is not functionally used. Without the RXCLK input
oscillating, the chip may not reset properly.
This is the MPEG asynchronous clock.
When the test mode pin is not asserted, this chip runs as specified. When the
test mode pin is asserted, the chip is in LSSD test mode. Transparent latches
become clocked latches and I/Os change to primary test inputs and test out-
puts. The precise connections are specified in the VHDL. This signal is asserted
high when in test mode.
Used by RISCWatch to halt the Power PC core for debug purposes. This does
not need to be in a TEST/NOSCAN I/O location.
These bits control the "find frequency" function which sets the range bits of the
PLL. Below is the encoded meaning of these bits.
000 = Enable internal register of these bits in CRSET
001 = Disable auto range function: set range to < 25.0MHz operation
010 = Disable auto range function: set range to 25.0MHz - 33.3MHz-011 = Dis-
100 = Enable auto range function for 19.44MHz
101 = Reserved
110 = Enable auto range function for 25.0MHz
111 = Enable auto range function for 32.0MHz
This input is the auto range known frequency input that is used to time the PCI
clock input. This should be connected to some oscillator on the card, for exam-
ple, the PHY oscillator. This is also used as the BIST clock. Without this input
oscillator, the chip will not run BIST nor will it properly reset; it is required for
proper operation.
When tied to ’1’, this input will cause the PLL to do a parametric testing at the
wafer and module level. Normal mode for this pin is a ’0’.
Filtered Vdd source to the PLL logic. See technology application notes for filter
circuit.
Minus active SELFTEST input. Normal mode is a ‘1’.
JTAG Test Reset provides an asynchronous initialization of the TAP controller.
JTAG Test Clock is used to clock state information and test data into and out of
the device during operation of the TAP.
JTAG Test Mode Select is used to control the state of the TAP controller in the
device. (LSSD test function - RARRYTCLKC - SC)
JTAG Test Data Input is used to serially shift test data and test instructions into
the device during TAP operation. (LSSD test function - CLKDIVTCLKC-SC)
able auto range function: set range to 50.0MHz operation
Pin Description
pnr25.chapt02.01
August 14, 2000
Preliminary