ibm3206k0424 ETC-unknow, ibm3206k0424 Datasheet - Page 540

• Manufacturer Part Number: ibm3206k0424
• Description: Ibm Processor For Network Resources
• Manufacturer: ETC-unknow

IBM3206K0424
IBM Processor for Network Resources
23: GPPHandler Architecture
Overview
All GPP handlers for the various chiplets have the following general register structure.
GPPHandler Architecture
Counter Registers
Every counter has an enable bit in the counter enable register (addr 2 or 3), and optionally up to two program-
mable thresholds. Each counter has an interrupt bit for overflow and up to two interrupt bits for threshold
crossing in the counter interrupt registers. For all counters in one handler there is one common
’read-on-the-fly register’ that is used to store the higher order bytes to obtain a correct readback value for
counters larger than eight bits. Counters are read-only registers; the count enable registers are read/write.
Note: COUNTER reading is independent of the counter length, given that a counter has address n as base,
reading address n or address n-1 both yield the least significant byte of the counter. Reading address n has
no influence on the counter, but reading address n-1 will reset the counter after the read. Reading address n
or n-1 will always latch the higher order bytes into the read on the fly register (before the optional automatic
reset). Counters can only be read and not written to. For a 16-bit counter, the most significant byte should be
read from ROFmid (address 0). For a 24-bit counter, the most significant byte is read from ROFhi (address 1),
the next byte from ROFmid (address 0). To completely read a 24-bit counter: first read least significant byte
from counter address n or n-1, then read ROFmid and ROFhi (address 0; address 1).
Reset Registers
Each handler has a two-bit reset register. Bit 0 is the chiplet reset control. This bit is active high after power
on reset, causing the chiplet to be disabled. Bit 1 is the chiplet halt signal, which for selected chiplets freezes
the state machines for diagnostic purposes. This is a read/write register.
Command Registers
The optional command register(s) will generate events to the chiplet. When a bit is written high by the micro-
processor, it will remain high for one chiplet clock cycle. Therefore, reading back a command register will
always read back zeroes. This is a read/write register.
GPPHandler Architecture
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Address Range
X’31 - 32’
X’33 - 37’
X’38 - 47’
X’48 - 57’
X’4 - 2F’
X’0 - 1’
X’2 - 3’
X’30’
Read on the Fly registers
Counter enable registers
Counters and counter threshold registers
Reset register
Command registers
Event latch registers (was called status)
Interrupt registers (addr=int reg, addr-1=int mask reg)
Configuration registers
Register Function
pnr25.chapt06.01
August 14, 2000
Preliminary