ibm3206k0424 ETC-unknow, ibm3206k0424 Datasheet - Page 401

• Manufacturer Part Number: ibm3206k0424
• Description: Ibm Processor For Network Resources
• Manufacturer: ETC-unknow

Preliminary
Debugging Register Access
This section is a very brief documentation of access that has been put in for the internal registers of RXQUE.
These addresses need not be written or read during normal operations.
13.20: RXQUE RXQ State Machine Variable Register
Main state variable for RXQUE processing state machine.
Length
Type
Address
Power On Value
Restrictions
13.21: RXQUE RXQ ENQ State Machine Variable Register
Main state variable for RXQUE processing state machine.
Length
Type
Address
Power On Value
Restrictions
pnr25.chapt05.01
August 14, 2000
Bit(s)
2
1
0
Receive bad frames
BCACH advice
Diagnostic mode
Name
4 bits
Read/Write
XXXX 1E80
X’00000000’
None
3 bits
Read/Write
XXXX 1E84
X’00000000’
None
When this bit is set, bad frame events (all error events), will be received in the normal
rxq defined in the LCD. All buffers are not freed, and the packet address is raised in the
event data.
When this bit is reset, bad frame events are routed to the rxq specified by the Error
Event Receive Queue Register. All packet based events will carry the LC address in
the event data instead of the packet address. All buffers are freed back to POOLS.
Note: This bit should only be changed sparingly because it changes the way packets
are freed and what is surfaced in an event (LCD vs. frame ptr). It should really only be
changed when the receive side is inactive.
This bit, when set, allows RXQUE to give BCACH cache fill advice based on events
that are dequeued.
When this bit is set or when the chip is disabled, the RXQUE entity is in diagnostic
mode and primitive execution is disabled.
Description
IBM Processor for Network Resources
Receive Queues (RXQUE)
Page 401 of 676
IBM3206K0424