ibm3206k0424 ETC-unknow, ibm3206k0424 Datasheet - Page 160

• Manufacturer Part Number: ibm3206k0424
• Description: Ibm Processor For Network Resources
• Manufacturer: ETC-unknow

IBM3206K0424
IBM Processor for Network Resources
3.3: DMAQS Head Pointer Registers
These registers point to the head element of the corresponding DMA queue. During normal operations, these
registers do not need to be read or written; they are used by the IBM3206K0424 to implement the DMA
queues. These registers are initialized when the DMAQS Lower Bound Registers for the corresponding DMA
queue is written.
Length
Type
Address
Power on Value
Restrictions
3.4: DMAQS Tail Pointer Registers
These registers point to the next free element of the corresponding DMA queue.
Length
Type
Address
Power on Value
Restrictions
DMA QUEUES (DMAQS)
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32 bits
Read/Write
Queue 0
Queue 1
Queue 2
X’00000000’
During normal operations, these registers are read only. They can only be written
when the diagnostic bit has been set in the DMAQS Control Register. The head
pointer registers are 4-byte aligned (low order two bits are always ’0’). Bits 31-17
are calculated internally and are not writable.
32 bits
Read/Write
Queue 0
Queue 1
Queue 2
X’00000000’
During normal operations, these registers are read only. They can only be written
when the diagnostic bit has been set in the DMAQS Control Register. The head
pointer registers are four-byte aligned (low order two bits are always ’0’). Bits 31-17
are calculated internally and are not writable.
608
688
708
60C
68C
70C
pnr25.chapt04.01
August 14, 2000
Preliminary