ibm3206k0424 ETC-unknow, ibm3206k0424 Datasheet - Page 240

• Manufacturer Part Number: ibm3206k0424
• Description: Ibm Processor For Network Resources
• Manufacturer: ETC-unknow

IBM3206K0424
IBM Processor for Network Resources
The Bus DRAM Cache Controller (BCACH)
Page 240 of 676
17-16
Bit(s)
15-8
7-0
25
24
23
22
21
20
19
18
Flush Cache Line 1
Flush Cache Line 0
Use RXQUE Advice
Ack RXQUE Immediately
Enable Ping Pong Buffer Support
Disable Locking on Collisions
Enable automatic flush
Force predictive fill/flush for
non-streaming accesses
Reserved
Predictive Fill Threshold
Timed Flush Time Out Value
Function
Setting this bit forces a flush of cache line 1 if it is dirty. This bit will be reset by the hard-
ware when the flush completes.
Setting this bit forces a flush of cache line 0 if it is dirty. This bit will be reset by the hard-
ware when the flush completes.
When set, advice from the receive queue entity causes the cache logic to fill a line with
the data from the start of the buffer that was just dequeued by the software. This should
improve performance by having the receive data available when the processor accesses
the buffer after the dequeue. To make best use of this feature, the code should access
the receive data shortly after the dequeue to avoid the data in the cache line from becom-
ing stale and being invalidated due to other cache functions. When reset, advice from the
receive queue entity will be ignored.
When reset, advice from the receive queue entity is acknowledged immediately even if
the cache is not able to perform the requested data fetch. In this case, the advice is lost,
and the cache will not fetch the data until the processor requests it again. When set, the
advice from the receive queue entity is not acknowledged until the cache has actually
latched the advice information. This guarantees that the advice will be used, but may
cause delays in the Receive Queue entity’s processing.
When reset, this bit disables the two-line ping pong feature associated with consistent
sequential cache accesses. When set, a series of sequential accesses to Packet Mem-
ory that would normally require more than two cache lines to be satisfied is limited to only
two cache lines, regardless of the length of the transfer. This feature is intended to
improves cache performance by preventing cache lines that contain the most recently
used processor data from being flushed due to a long streaming access.
When set, this bit prevents detected collisions from locking up the memory control entity.
When set, this bit enables the automatic flush feature of the cache. The auto flush fea-
ture forces a flush of a cache line to be performed if a sequential write of the last 2 loca-
tions in the cache line is detected.
When set, this bit forces the predictive fill/flush logic to operate on all accesses of the
cache rather than just streaming accesses. When reset, the predictive fill logic will only
be activated for streaming accesses in the cache.
Reserved.
These bits set the threshold at which a predictive fill will be initiated. If all of these bits are
set to ‘1’, a predictive fill will be initiated on the first streaming access of a cache line,
regardless of which byte in the line is accessed. If this field is set to X’3F’ a predictive fill
will be initiated on any streaming access of bytes at offset X’2’ through X’7’ in the cache
line. If this field is set to X’03’ a predictive fill will be initiated on any streaming access of
bytes at offset X’6’ or X’7’ in the cache line. Setting the field to all ’0’s will disable predic-
tive fills.
These bits control the time-out value used to monitor dirty cache lines for inactivity. The
value loaded into these eight bits is the number of 240 ns ticks that can occur without any
activity in a dirty cache line before the cache logic will force a flush of the line to main
memory. Setting these bits to all ’0’s disables the timed flush feature.
Description
pnr25.chapt04.01
August 14, 2000
Preliminary