ibm3206k0424 ETC-unknow, ibm3206k0424 Datasheet - Page 49

• Manufacturer Part Number: ibm3206k0424
• Description: Ibm Processor For Network Resources
• Manufacturer: ETC-unknow

Preliminary
NPBUS Pin Descriptions
pnr25.chapt02.01
August 14, 2000
Quantity
1. S/T/S = a sustained tri-state pin owned and driven by one and only one agent at a time. The agent that drives the S/T/S pin low
63
1
1
1
1
1
1
must drive it high for at least one clock before letting it float. A new agent cannot start driving a S/T/S signal any sooner that one
clock after the previous owner tri-states it. A pullup is required to sustain the inactive state until another agent drives it and must be
provided by the central resource.
PBADDR16
PBnEPRM
Pin Name
ENSTATE
PBnPHY1
PBnPHY2
PBALE1
PBALE2
(63-0)
Input/Output
Output
Output
Output
Output
Output
Output
Output
EPROM Select
Address Send 16
Select PHY 1
Select PHY 2
Address Latch Enable 1
Address Latch Enable 2
Pin Function
When low, indicates that the IBM3206K0424 has selected PHY 1 to
write to control registers inside PHY 1 or to read either the control
or status registers.
When low, indicates that the IBM3206K0424 has selected PHY 2 to
write to control registers inside PHY 2 or to read either the control
or status registers. See NPBUS Control Register on page 428 for
more details.
If configured, this pin can also be odd parity across the eight-bit
wide bidirectional data bus. It can also be configured as MPMDSEL
- this control pin, under register bit control, can drive a logical value
out. The intention is to select between the different PMD types on
the 155 Mb/s copper card (UTP verses STP). If it is in cascade
mode, this bit functions as PIDSELO (+idsel out), which the primary
IBM3206K0424 will drive to the secondary IBM3206K0424 when
trying to update configuration space via configuration cycles. This
multiplexed pin also carries the PBDATAP signal.
When programmed, drives out the real-time state-of-entity state
machines, counters, etc. for debug purposes. The (47-32) bits of
this bus are also PBADDR(15 - 0), which are the address lines for
the external parallel EPROM or PHY. Additionally, bits 47 - 40 can
be used as bi-directional data bus bits to extend the PBDATA bus
by providing bits 15 - 8 of this bus. This allows operation with PHY
parts that have a fixed 16-bit data but limits the addressing to this
PHY to only eight address bits. (LSSD test function - scanout(13 to
0) -SO -BDY)
When low, indicates that the IBM3206K0424 has selected the
external EPROM to read from. After reset, the IBM3206K0424 will
start accessing the optional on-card ROM/EPROM and do the chip
initialization function if it does not find a serial EPROM attached.
When high, indicates that the IBM3206K0424 has generated an
address on the PBDATA bus and should be latched by either a
PHY that supports this muxing or an external octal latch TTL part.
For an external EPROM, it will also latch bits 7-0 of the address for
an external EPROM access.
When high, indicates that the IBM3206K0424 has generated an
address on the PBDATA bus and should be latched by an external
octal latch TTL part that holds bits 15-8 of the address for an exter-
nal EPROM or PHY access.
Supplies address 16 to an external EPROM. The pin will also func-
tion as PBALE3, an address latch enable, that indicates that the
IBM3206K0424 has generated an address on the PBDATA bus
and should be latched by an external octal latch TTL part that holds
bits 23-16 of the address for an external EPROM access. The
mechanism used to set this mode is to put a pull-down resistor on
this pin. At reset time, it will be detected and set this bit in PBALE3
mode. Otherwise it will be in PBADDR16 mode.
IBM Processor for Network Resources
Pin Description
IBM3206K0424
Page 49 of 676
NPBUS