ibm3206k0424 ETC-unknow, ibm3206k0424 Datasheet - Page 441

• Manufacturer Part Number: ibm3206k0424
• Description: Ibm Processor For Network Resources
• Manufacturer: ETC-unknow

Preliminary
Debugging Register Access
16.9: CHKSM Internal State
Internal state of checksum.
Note: This register should not be written unless specifically directed to do so by IBM technical support.
Length
Type
Address
Power On Value
Restrictions
pnr25.chapt05.01
August 14, 2000
bit(s)
7
6
5
4
3
2
1
0
RP-ADD -- Ripple Addend
CL-IP -- Clear IP
RP -- Ripple
MS -- Memory Select
RW -- R/-W Test Mode
TM -- Test Mode
ET -- Enable TCP Checksum
Updates
EE -- Enable Entity CHKSM
Name
3 bits
Read/Write
XXXX 0A3c
X’00000000’
None
When this bit is set, the ripple base register counts up by one. When this bit is cleared,
the ripple base register counts up by eight.
When this bit is written, it will clear the CHKSM TCP/IP Checksum Data Register and
itself. The result of this will be that this bit will never be read as a ’1’. The internal align-
ment is also cleared.
When this bit is set, a ripple pattern will be used in both the read and write test modes.
The ripple pattern is used instead of the constant test pattern. When this bit is reset,
the constant test pattern is used for the test mode data.
When this bit is set, all CHKSM memory accesses are to the Control Memory. When
this bit is cleared, all CHKSM memory accesses are to the Packet Memory.
When this bit is set, the entity will take the data that is read and compare it to the
test/ripple pattern.
When this bit is reset, the checksum entity will write data using the test/ripple pattern to
the DRAM.
When this bit is set, the entity will take the data that is read and compare it to the
test/ripple pattern, or will write data using the test/ripple pattern to the DRAM depend-
ing on the setting of the RW bit. In both cases, the reading or writing will continue until
either an error is encountered or the CHKSM Read/Write Count Register counts down
to ’0’.
When this bit is reset, the checksum entity will operate as described by the other bits.
Test and CHKSM modes are mutually exclusive, and test mode takes precedence.
When this bit is set, the entity will collect the TCP checksum in the CHKSM TCP/IP
Checksum Data Register.
When this bit is reset, the CHKSM TCP/IP Checksum Data Register will not be
changed by data that is read from the DRAM.
Test and CHKSM modes are mutually exclusive, and test mode takes precedence.
When this bit is set, the entity will run as specified.
When this bit is reset, the entity will not run.
On-chip Checksum and DRAM Test Support (CHKSM)
Description
IBM Processor for Network Resources
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IBM3206K0424