at91sam9263 ATMEL Corporation, at91sam9263 Datasheet - Page 671

no-image

at91sam9263

Manufacturer Part Number
at91sam9263
Description
At91 Arm Thumb Microcontrollers
Manufacturer
ATMEL Corporation
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AT91SAM9263
Manufacturer:
AT
Quantity:
1
Part Number:
at91sam9263-CJ
Manufacturer:
ATMEL
Quantity:
181
Part Number:
at91sam9263-CU
Manufacturer:
ATMEL
Quantity:
132
Part Number:
at91sam9263-EK
Manufacturer:
Atmel
Quantity:
135
Part Number:
at91sam9263B-CU
Manufacturer:
IDT
Quantity:
1 043
Part Number:
at91sam9263B-CU
Manufacturer:
Atmel
Quantity:
10 000
Part Number:
at91sam9263B-CU
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
Part Number:
at91sam9263B-CU-100
Manufacturer:
ATMEL
Quantity:
1 000
Part Number:
at91sam9263B-CU-100
Manufacturer:
ATMEL
Quantity:
3 060
Part Number:
at91sam9263B-CU-100
Manufacturer:
Atmel
Quantity:
10 000
Figure 37-9. Disabling Low-power Mode
37.7
37.7.1
6249D–ATARM–20-Dec-07
Functional Description
(CAN_MSRx)
CAN Controller Initialization
(CAN_SR)
WAKEUP
(CAN_MR)
(CAN_SR)
CAN BUS
SLEEP
MRDY
LPM
The CAN controller synchronizes itself with the bus activity by checking for eleven consecutive
“recessive” bits. Once synchronized, the WAKEUP signal in the CAN_SR register is set.
Depending on the corresponding mask in the CAN_IMR register, an interrupt is generated while
WAKEUP is set. The SLEEP signal in the CAN_SR register is automatically cleared once
WAKEUP is set. WAKEUP signal is automatically cleared once SLEEP is set.
If no message is being sent on the bus, then the CAN controller is able to send a message
eleven bit times after disabling Low-power Mode.
If there is bus activity when Low-power mode is disabled, the CAN controller is synchronized
with the bus activity in the next interframe. The previous message is lost (see
After power-up reset, the CAN controller is disabled. The CAN controller clock must be activated
by the Power Management Controller (PMC) and the CAN controller interrupt line must be
enabled by the interrupt controller (AIC).
The CAN controller must be initialized with the CAN network parameters. The CAN_BR register
defines the sampling point in the bit time period. CAN_BR must be set before the CAN controller
is enabled by setting the CANEN field in the CAN_MR register.
The CAN controller is enabled by setting the CANEN flag in the CAN_MR register. At this stage,
the internal CAN controller state machine is reset, error counters are reset to 0, error flags are
reset to 0.
Once the CAN controller is enabled, bus synchronization is done automatically by scanning
eleven recessive bits. The WAKEUP bit in the CAN_SR register is automatically set to 1 when
the CAN controller is synchronized (WAKEUP and SLEEP are stuck at 0 after a reset).
The CAN controller can start listening to the network in Autobaud Mode. In this case, the error
counters are locked and a mailbox may be configured in Receive Mode. By scanning error flags,
– Enable the CAN Controller clock. This is done by programming the Power
– Clear the LPM field in the CAN_MR register
Management Controller (PMC).
Message lost
Interframe synchronization
Bus Activity Detected
Message x
AT91SAM9263 Preliminary
Figure
37-9).
671

Related parts for at91sam9263