at91sam9263 ATMEL Corporation, at91sam9263 Datasheet - Page 242

• Manufacturer Part Number: at91sam9263
• Description: At91 Arm Thumb Microcontrollers
• Manufacturer: ATMEL Corporation

22.5
22.5.1
Figure 22-2. Write Burst, 32-bit SDRAM Access
242
SDRAMC_A[12:0]
Functional Description
D[31:0]
SDWE
SDCS
SDCK
AT91SAM9263 Preliminary
RAS
CAS
SDRAM Controller Write Cycle
The SDRAM Controller allows burst access or single access. In both cases, the SDRAM control-
ler keeps track of the active row in each bank, thus maximizing performance. To initiate a burst
access, the SDRAM Controller uses the transfer type signal provided by the master requesting
the access. If the next access is a sequential write access, writing to the SDRAM device is car-
ried out. If the next access is a write-sequential access, but the current access is to a boundary
page, or if the next access is in another row, then the SDRAM Controller generates a precharge
command, activates the new row and initiates a write command. To comply with SDRAM timing
parameters, additional clock cycles are inserted between precharge/active (t
active/write (t
Configuration Register” on page
Row n
t
RCD
= 3
col a
RCD
Dna
) commands. For definition of these timing parameters, refer to the
col b
Dnb
col c
Dnc
253. This is described in
col d
Dnd
col e
Dne
col f
Dnf
col g
Dng
Figure 22-2
col h
Dnh
col i
Dni
below.
col j
Dnj
6249D–ATARM–20-Dec-07
RP
) commands and
col k
Dnk
“SDRAMC
col l
Dnl