at91sam9263 ATMEL Corporation, at91sam9263 Datasheet - Page 255

• Manufacturer Part Number: at91sam9263
• Description: At91 Arm Thumb Microcontrollers
• Manufacturer: ATMEL Corporation

22.6.4
Register Name:
Access Type:
Reset Value:
• LPCB: Low-power Configuration Bits
• PASR: Partial Array Self-refresh (only for low-power SDRAM)
PASR parameter is transmitted to the SDRAM during initialization to specify whether only one quarter, one half or all banks
of the SDRAM array are enabled. Disabled banks are not refreshed in self-refresh mode. This parameter must be set
according to the SDRAM device specification.
After initialization, as soon as PASR field is modified and self-refresh mode is activated, the Extended Mode Register is
accessed automatically and PASR bits are updated before entry in self-refresh mode.
• TCSR: Temperature Compensated Self-Refresh (only for low-power SDRAM)
TCSR parameter is transmitted to the SDRAM during initialization to set the refresh interval during self-refresh mode
depending on the temperature of the low-power SDRAM. This parameter must be set according to the SDRAM device
specification.
After initialization, as soon as TCSR field is modified and self-refresh mode is activated, the Extended Mode Register is
accessed automatically and TCSR bits are updated before entry in self-refresh mode.
• DS: Drive Strength (only for low-power SDRAM)
DS parameter is transmitted to the SDRAM during initialization to select the SDRAM strength of data output. This parame-
ter must be set according to the SDRAM device specification.
6249D–ATARM–20-Dec-07
31
23
15
–
–
–
7
–
00
01
10
11
SDRAMC Low Power Register
Low Power Feature is inhibited: no Power-down, Self-refresh or Deep Power-down command is issued to the
SDRAM device.
The SDRAM Controller issues a Self-refresh command to the SDRAM device, the SDCLK clock is deactivated
and the SDCKE signal is set low. The SDRAM device leaves the Self Refresh Mode when accessed and enters
it after the access.
The SDRAM Controller issues a Power-down Command to the SDRAM device after each access, the SDCKE
signal is set to low. The SDRAM device leaves the Power-down Mode when accessed and enters it after the
access.
The SDRAM Controller issues a Deep Power-down command to the SDRAM device. This mode is unique to
low-power SDRAM.
30
22
14
SDRAMC_LPR
Read/Write
0x0
–
–
–
6
PASR
29
21
13
–
–
5
TIMEOUT
28
20
12
–
–
4
27
19
11
–
–
3
–
AT91SAM9263 Preliminary
DS
26
18
10
–
–
2
–
25
17
–
–
9
1
TCSR
LPCB
24
16
–
–
8
0
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