at91sam9263 ATMEL Corporation, at91sam9263 Datasheet - Page 1030

• Manufacturer Part Number: at91sam9263
• Description: At91 Arm Thumb Microcontrollers
• Manufacturer: ATMEL Corporation

49.2.8.2
49.2.8.3
1030
AT91SAM9263 Preliminary
LCD Periodic Bad Pixels
24-bit Packed Mode
leads to reset DMA pointers but not FIFO pointers, the displayed image is shifted.
Problem Fix/Workaround
Apply the following sequence:
LCD periodic bad pixels is due to mis-aligned DMA base address in frame buffer. LCD DMA per-
forms bursts to read memory. These bursts must not cross 1 Kb AMBA boundary.
Problem Fix/Workaround
The burst size in 32-bit words is programmed by field BRSTLN in DMA_FRMCFG register.
The LCD DMA Base Address is programmed in DMA_BADDR1 register.
DMA Base Address must be programmed with a value aligned onto LCD DMA burst size.
e.g.:
BRSTLN = 15
For a 16-word burst, the LCD DMA Base Address offset must be 0x0, 0x40, 0x80 or 0xc0.
BRSTLN = 3
For a 4-word burst, the LCD DMA Base Address offset must be 0x0, 0x10, ..., 0xf0.
LCD DMA Base Address and LCD DMA burst size must be selected with care in 24-bit packed
mode. A 32-bit word contains some bits of a pixel and some bits of the following. If LCD DMA
Base Address is not aligned with a pixel start, the colors will be modified.
Respect "LCD periodic bad pixels" erratum constrains lead to select the LCD DMA Base
Address regarding the LCD DMA burst size.
Problem Fix/Workaround
LCD DMA Base Address is to be set on a pixel start, every three 32-bit word.
The offset of the LCD DMA Base Address must be a multiple of 0x30 plus 0x0, 0xc, 0x18 or
0x24. (0x0, 0xc, 0x18, 0x24, 0x30, 0x3c, 0x48, 0x54, 0x60,0x6c, 0x78, 0x84, 0x90, 0x9c, 0xa8,
0xb4, 0xc0 ...)
e.g. regarding the bursts size:
• DMA disable
• Wait for DMABUSY
• DMA reset
• DMA enable
• LCD power off
• DMA disable
• Wait for DMABUSY
• DMA reset
• LCD power on
• DMA enable.
6249D–ATARM–20-Dec-07