at91sam9263 ATMEL Corporation, at91sam9263 Datasheet - Page 329

• Manufacturer Part Number: at91sam9263
• Description: At91 Arm Thumb Microcontrollers
• Manufacturer: ATMEL Corporation

24.4.23
Name: DMAC_ChEnReg
Access: Read/Write
Reset: 0x0
• CH_EN[1:0]
0 = Disable the Channel
1 = Enable the Channel
Enables/Disables the channel. Setting this bit enables a channel, clearing this bit disables the channel.
The DMAC_ChEnReg.CH_EN bit is automatically cleared by hardware to disable the channel after the last AMBA transfer
of the DMA transfer to the destination has completed.Software can therefore poll this bit to determine when a DMA transfer
has completed.
• CH_EN_WE[9:8]
The channel enable bit, CH_EN, is only written if the corresponding channel write enable bit, CH_EN_WE, is asserted on
the same AMBA write transfer.
For example, writing 0x101 writes a 1 into DMAC_ChEnReg[0], while DMAC_ChEnReg[7:1] remains unchanged.
6249D–ATARM–20-Dec-07
31
23
15
–
–
–
7
–
DMAC Channel Enable Register
30
22
14
–
–
–
6
–
29
21
13
–
–
–
5
–
28
20
12
–
–
–
4
–
27
19
11
–
–
–
3
–
AT91SAM9263 Preliminary
26
18
10
–
–
–
2
–
CH_EN_WE1
CH_EN1
25
17
–
–
9
1
CH_EN_WE0
CH_EN0
24
16
–
–
8
0
329