at91sam9263 ATMEL Corporation, at91sam9263 Datasheet - Page 312

• Manufacturer Part Number: at91sam9263
• Description: At91 Arm Thumb Microcontrollers
• Manufacturer: ATMEL Corporation

AT91SAM9263 Preliminary
1 = Software handshaking interface. Hardware-initiated transaction requests are ignored.
If the source peripheral is memory, then this bit is ignored.
• LOCK_CH_L: Channel Lock Level
Indicates the duration over which DMAC_CFGx.LOCK_CH bit applies.
00 = Over complete DMA transfer
01 = Over complete DMA block transfer
1x = Over complete DMA transaction
• LOCK_B_L: Bus Lock Level
Indicates the duration over which DMAC_CFGx.LOCK_B bit applies.
00 = Over complete DMA transfer
01 = Over complete DMA block transfer
1x = Over complete DMA transaction
• LOCK_CH: Channel Lock Bit
When the channel is granted control of the master bus interface and if the DMAC_CFGx.LOCK_CH bit is asserted, then no
other channels are granted control of the master bus interface for the duration specified in DMAC_CFGx.LOCK_CH_L.
Indicates to the master bus interface arbiter that this channel wants exclusive access to the master bus interface for the
duration specified in DMAC_CFGx.LOCK_CH_L.
• LOCK_B: Bus Lock Bit
When active, the AMBA bus master signal hlock is asserted for the duration specified in DMAC_CFGx.LOCK_B_L.
• DS_HS_POL: Destination Handshaking Interface Polarity
0 = Active high
1 = Active low
• SR_HS_POL: Source Handshaking Interface Polarity
0 = Active high
1 = Active low
• MAX_ABRST: Maximum AMBA Burst Length
Maximum AMBA burst length that is used for DMA transfers on this channel. A value of ‘0’ indicates that software is not lim-
iting the maximum AMBA burst length for DMA transfers on this channel.
• RELOAD_SR: Automatic Source Reload
The DMAC_SARx register can be automatically reloaded from its initial value at the end of every block for multi-block trans-
fers. A new block transfer is then initiated.
• RELOAD_DS: Automatic Destination Reload
The DMAC_DARx register can be automatically reloaded from its initial value at the end of every block for multi-block
transfers. A new block transfer is then initiated.
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