at91sam9263 ATMEL Corporation, at91sam9263 Datasheet - Page 238

• Manufacturer Part Number: at91sam9263
• Description: At91 Arm Thumb Microcontrollers
• Manufacturer: ATMEL Corporation

22.3
22.3.1
22.3.2
Table 22-2.
Table 22-3.
Table 22-4.
Notes:
238
27
27
27
Bk[1:0]
26
26
26
Bk[1:0]
Bk[1:0]
Application Example
1. M[1:0] is the byte address inside a 32-bit word.
2. Bk[1] = BA1, Bk[0] = BA0.
AT91SAM9263 Preliminary
25
25
25
Software Interface
32-bit Memory Data Bus Width
Bk[1:0]
Bk[1:0]
Bk[1:0]
24
24
24
SDRAM Configuration Mapping: 2K Rows, 256/512/1024/2048 Columns
SDRAM Configuration Mapping: 4K Rows, 256/512/1024/2048 Columns
SDRAM Configuration Mapping: 8K Rows, 256/512/1024/2048 Columns
Bk[1:0]
Bk[1:0]
Bk[1:0]
23
23
23
Bk[1:0]
Bk[1:0]
22
22
22
Bk[1:0]
The SDRAM address space is organized into banks, rows, and columns. The SDRAM controller
allows mapping different memory types according to the values set in the SDRAMC configura-
tion register.
The SDRAM Controller’s function is to make the SDRAM device access protocol transparent to
the user.
user in correlation with the device structure. Various configurations are illustrated.
21
21
21
20
20
20
Row[12:0]
Row[11:0]
Table 22-2
19
19
19
Row[10:0]
Row[12:0]
Row[11:0]
18
18
18
Row[10:0]
Row[12:0]
Row[11:0]
17
17
17
Row[10:0]
Row[12:0]
to
Row[11:0]
16
16
16
Table 22-7
Row[10:0]
15
15
15
CPU Address Line
CPU Address Line
CPU Address Line
14
14
14
illustrate the SDRAM device memory mapping seen by the
13
13
13
12
12
12
11
11
11
10
10
10
9
9
9
8
Column[10:0]
8
8
Column[10:0]
Column[10:0]
Column[9:0]
Column[9:0]
Column[9:0]
7
7
7
Column[8:0]
Column[8:0]
Column[8:0]
Column[7:0]
Column[7:0]
Column[7:0]
6
6
6
5
5
5
4
4
4
6249D–ATARM–20-Dec-07
3
3
3
2
2
2
1
1
1
M[1:0]
M[1:0]
M[1:0]
M[1:0]
M[1:0]
M[1:0]
M[1:0]
M[1:0]
M[1:0]
M[1:0]
M[1:0]
M[1:0]
0
0
0