at91sam9263 ATMEL Corporation, at91sam9263 Datasheet - Page 501

• Manufacturer Part Number: at91sam9263
• Description: At91 Arm Thumb Microcontrollers
• Manufacturer: ATMEL Corporation

32.6.5
Register Name:
Access Type:
• TXCOMP: Transmission Completed
0 = During the length of the current frame.
1 = When both holding and shift registers are empty and STOP condition has been sent, or when MSEN is set (enable
TWI).
• RXRDY: Receive Holding Register Ready
0 = No character has been received since the last TWI_RHR read operation.
1 = A byte has been received in the TWI_RHR since the last read.
• TXRDY: Transmit Holding Register Ready
0 = The transmit holding register has not been transferred into shift register. Set to 0 when writing into TWI_THR register.
1 = As soon as data byte is transferred from TWI_THR to internal shifter or if a NACK error is detected, TXRDY is set at the
same time as TXCOMP and NACK. TXRDY is also set when MSEN is set (enable TWI).
• NACK: Not Acknowledged
0 = Each data byte has been correctly received by the far-end side TWI slave component.
1 = A data byte has not been acknowledged by the slave component. Set at the same time as TXCOMP. Reset after read.
501
31
23
15
–
–
–
7
–
AT91SAM9263 Preliminary
TWI Status Register
30
22
14
TWI_SR
–
–
–
6
–
Read-only
29
21
13
–
–
–
5
–
28
20
12
–
–
–
4
–
27
19
11
–
–
–
3
–
TXRDY
26
18
10
–
–
–
2
RXRDY
25
17
–
–
9
–
1
6249D–ATARM–20-Dec-07
TXCOMP
NACK
24
16
–
–
8
0