at91sam9263 ATMEL Corporation, at91sam9263 Datasheet - Page 14

• Manufacturer Part Number: at91sam9263
• Description: At91 Arm Thumb Microcontrollers
• Manufacturer: ATMEL Corporation

6.2
6.3
6.4
6.5
7. Processor and Architecture
7.1
14
Test Pin
Reset Pins
PIO Controllers
Shutdown Logic Pins
ARM926EJ-S Processor
AT91SAM9263 Preliminary
The NTRST signal is described in
All JTAG signals except JTAGSEL (VDDBU) are supplied with VDDIOP0.
The TST pin is used for manufacturing test purposes when asserted high. It integrates a perma-
nent pull-down resistor of about 15 kΩ to GNDBU, so that it can be left unconnected for normal
operations. Driving this line at a high level leads to unpredictable results.
This pin is supplied with VDDBU.
NRST is an open-drain output integrating a non-programmable pull-up resistor. It can be driven
with voltage at up to VDDIOP0.
NTRST is an input which allows reset of the JTAG Test Access port. It has no action on the
processor.
As the product integrates power-on reset cells, which manage the processor and the JTAG
reset, the NRST and NTRST pins can be left unconnected.
The NRST and NTRST pins both integrate a permanent pull-up resistor of 100 kΩ minimum to
VDDIOP0.
The NRST signal is inserted in the Boundary Scan.
All the I/O lines managed by the PIO Controllers integrate a programmable pull-up resistor of
100 kΩ typical. Programming of this pull-up resistor is performed independently for each I/O line
through the PIO Controllers.
After reset, all the I/O lines default as inputs with pull-up resistors enabled, except those which
are multiplexed with the External Bus Interface signals that require to be enabled as Peripheral
at reset. This is explicitly indicated in the column “Reset State” of the PIO Controller multiplexing
tables on
The SHDN pin is an output only, which is driven by the Shutdown Controller.
The pin WKUP is an input only. It can accept voltages only between 0V and VDDBU.
• RISC Processor based on ARM v5TEJ Harvard Architecture with Jazelle technology for Java
• Two Instruction Sets
• DSP Instruction Extensions
• 5-stage Pipeline Architecture
acceleration
– ARM High-performance 32-bit Instruction Set
– Thumb High Code Density 16-bit Instruction Set
page 35
and following.
Section
6.3.
6249D–ATARM–20-Dec-07