at91sam9263 ATMEL Corporation, at91sam9263 Datasheet - Page 50

• Manufacturer Part Number: at91sam9263
• Description: At91 Arm Thumb Microcontrollers
• Manufacturer: ATMEL Corporation

11.3.7
50
AT91SAM9263 Preliminary
ARM9EJ-S Registers
Mode changes may be made under software control, or may be brought about by external inter-
rupts or exception processing. Most application programs execute in User Mode. The non-user
modes, known as privileged modes, are entered in order to service interrupts or exceptions or to
access protected resources.
The ARM9EJ-S core has a total of 37 registers:
Table 11-1
Table 11-1.
The ARM state register set contains 16 directly-accessible registers, r0 to r15, and an additional
register, the Current Program Status Register (CPSR). Registers r0 to r13 are general-purpose
• Supervisor mode is a protected mode for the operating system
• Abort mode is entered after a data or instruction prefetch abort
• System mode is a privileged user mode for the operating system
• Undefined mode is entered when an undefined instruction exception occurs
• 31 general-purpose 32-bit registers
• 6 32-bit status registers
System Mode
User and
CPSR
R10
R11
R12
R13
R14
PC
R0
R1
R2
R3
R4
R5
R6
R7
R8
R9
shows all the registers in all modes.
ARM9TDMI
Supervisor
SPSR_SVC
R13_SVC
R14_SVC
CPSR
Mode
R10
R11
R12
PC
R0
R1
R2
R3
R4
R5
R6
R7
R8
R9
®
Modes and Registers Layout
SPSR_ABORT
R13_ABORT
R14_ABORT
Abort Mode
CPSR
R10
R11
R12
PC
R0
R1
R2
R3
R4
R5
R6
R7
R8
R9
SPSR_UNDEF
R13_UNDEF
R14_UNDEF
Undefined
CPSR
Mode
R10
R11
R12
PC
R0
R1
R2
R3
R4
R5
R6
R7
R8
R9
Interrupt Mode
Mode-specific banked registers
SPSR_IRQ
R13_IRQ
R14_IRQ
CPSR
R10
R11
R12
R0
R1
R2
R3
R4
R5
R6
R7
R8
R9
PC
6249D–ATARM–20-Dec-07
Fast Interrupt
SPSR_FIQ
R10_FIQ
R11_FIQ
R12_FIQ
R13_FIQ
R14_FIQ
R8_FIQ
R9_FIQ
CPSR
Mode
R0
R1
R2
R3
R4
R5
R6
R7
PC