at91sam9263 ATMEL Corporation, at91sam9263 Datasheet - Page 305

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at91sam9263

Manufacturer Part Number
at91sam9263
Description
At91 Arm Thumb Microcontrollers
Manufacturer
ATMEL Corporation
Datasheet

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24.4.2
Name: DMAC_DARx
Access: Read/Write
Reset: 0x0
The address offset for each channel is: 0x08+[x * 0x58]
For example, DAR0: 0x008, DAR1: 0x060, etc.
• DADD: Destination Address of DMA transfer
The starting AMBA destination address is programmed by software before the DMA channel is enabled or by a LLI update
before the start of the DMA transfer. As the DMA transfer is in progress, this register is updated to reflect the destination
address of the current AMBA transfer.
Updated after each destination AMBA transfer. The DINC field in the DMAC_CTLx register determines whether the
address increments, decrements or is left unchanged on every destination AMBA transfer throughout the block transfer.
6249D–ATARM–20-Dec-07
31
23
15
7
Channel x Destination Address Register
30
22
14
6
29
21
13
5
28
20
12
4
DADD
DADD
DADD
DADD
27
19
11
3
AT91SAM9263 Preliminary
26
18
10
2
25
17
9
1
24
16
8
0
305

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