at91sam9263 ATMEL Corporation, at91sam9263 Datasheet - Page 300

• Manufacturer Part Number: at91sam9263
• Description: At91 Arm Thumb Microcontrollers
• Manufacturer: ATMEL Corporation

24.3.6.1
6249D–ATARM–20-Dec-07
Abnormal Transfer Termination
When DMAC_CTLx.SRC_TR_WIDTH is less than DMAC_CTLx.DST_TR_WIDTH and the
DMAC_CFGx.CH_SUSP bit is high, the DMAC_CFGx.FIFO_EMPTY is asserted once the con-
tents of the FIFO do not permit a single word of DMAC_CTLx.DST_TR_WIDTH to be formed.
However, there may still be data in the channel FIFO but not enough to form a single transfer of
DMAC_CTLx.DST_TR_WIDTH width. In this configuration, once the channel is disabled, the
remaining data in the channel FIFO are not transferred to the destination peripheral. It is permit-
t e d t o r e m o v e t h e c h a n n e l f r o m t h e s u s p e n s i o n s t a t e b y w r i t i n g a ‘ 0 ’ t o t h e
DMAC_CFGx.CH_SUSP register. The DMA transfer completes in the normal manner.
Note:
A DMAC DMA transfer may be terminated abruptly by software by clearing the channel enable
bit, DMAC_ChEnReg.CH_EN. This does not mean that the channel is disabled immediately
after the DMAC_ChEnReg.CH_EN bit is cleared over the AHB slave interface. Consider this as
a request to disable the channel. The DMAC_ChEnReg.CH_EN must be polled and then it must
be confirmed that the channel is disabled by reading back 0. A case where the channel is not be
disabled after a channel disable request is where either the source or destination has received a
split or retry response. The DMAC must keep re-attempting the transfer to the system HADDR
that originally received the split or retry response until an OKAY response is returned. To do oth-
erwise is an AMBA protocol violation.
Software may terminate all channels abruptly by clearing the global enable bit in the DMAC Con-
figuration Register (DMAC_DmaCfgReg[0]). Again, this does not mean that all channels are
disabled immediately after the DMAC_DmaCfgReg[0] is cleared over the AHB slave interface.
Consider this as a request to disable all channels. The DMAC_ChEnReg must be polled and
then it must be confirmed that all channels are disabled by reading back ‘0’.
Note:
Note:
3. The DMAC_ChEnReg.CH_EN bit can then be cleared by software once the channel
FIFO is empty.
If a channel is disabled by software, an active single or burst transaction is not guaranteed to
receive an acknowledgement.
If the channel enable bit is cleared while there is data in the channel FIFO, this data is not sent to
the destination peripheral and is not present when the channel is re-enabled. For read sensitive
source peripherals such as a source FIFO this data is therefore lost. When the source is not a
read sensitive device (i.e., memory), disabling a channel without waiting for the channel FIFO to
empty may be acceptable as the data is available from the source peripheral upon request and is
not lost.
If a channel is disabled by software, an active single or burst transaction is not guaranteed to
receive an acknowledgement.
AT91SAM9263 Preliminary
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