at91sam9263 ATMEL Corporation, at91sam9263 Datasheet - Page 407

• Manufacturer Part Number: at91sam9263
• Description: At91 Arm Thumb Microcontrollers
• Manufacturer: ATMEL Corporation

Figure 29-4. Start Bit Detection
Figure 29-5. Character Reception
29.4.2.3
Figure 29-6. Receiver Ready
29.4.2.4
Figure 29-7. Receiver Overrun
29.4.2.5
6249D–ATARM–20-Dec-07
Receiver Ready
Receiver Overrun
Parity Error
Example: 8-bit, parity enabled 1 stop
Sampling
RXRDY
Sampling Clock
RXRDY
OVRE
DRXD
DRXD
DRXD
Baud Rate
DRXD
Clock
S
S
When a complete character is received, it is transferred to the DBGU_RHR and the RXRDY sta-
tus bit in DBGU_SR (Status Register) is set. The bit RXRDY is automatically cleared when the
receive holding register DBGU_RHR is read.
If DBGU_RHR has not been read by the software (or the Peripheral Data Controller) since the
last transfer, the RXRDY bit is still set and a new character is received, the OVRE status bit in
DBGU_SR is set. OVRE is cleared when the software writes the control register DBGU_CR with
the bit RSTSTA (Reset Status) at 1.
Each time a character is received, the receiver calculates the parity of the received data bits, in
accordance with the field PAR in DBGU_MR. It then compares the result with the received parity
0.5 bit
period
D0
D0
True Start Detection
D1
D1
period
D2
1 bit
D2
D3
D0
D3
D4
D4
D1
D5
D5
D6
D6
True Start
Detection
D2
D7
D7
P
P
D3
stop
S
S
D4
Read DBGU_RHR
D0
D0
D1
D1
AT91SAM9263 Preliminary
D5
D2
D2
D3
D3
D6
D4
D4
D5
D5
D7
D6
D6
Parity Bit
D7
D7
P
P
stop
Stop Bit
D0
RSTSTA
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