at91sam9263 ATMEL Corporation, at91sam9263 Datasheet - Page 245

• Manufacturer Part Number: at91sam9263
• Description: At91 Arm Thumb Microcontrollers
• Manufacturer: ATMEL Corporation

22.5.4
Figure 22-5. Refresh Cycle Followed by a Read Access
6249D–ATARM–20-Dec-07
SDRAMC_A[12:0]
D[31:0]
SDWE
(input)
SDCS
SDCK
RAS
CAS
SDRAM Controller Refresh Cycles
Row n
col c col d
Dnb
Dnc
An auto-refresh command is used to refresh the SDRAM device. Refresh addresses are gener-
ated internally by the SDRAM device and incremented after each auto-refresh automatically.
The SDRAM Controller generates these auto-refresh commands periodically. An internal timer is
loaded with the value in the register SDRAMC_TR that indicates the number of clock cycles
between refresh cycles.
A refresh error interrupt is generated when the previous auto-refresh command did not perform.
It is acknowledged by reading the Interrupt Status Register (SDRAMC_ISR).
When the SDRAM Controller initiates a refresh of the SDRAM device, internal memory accesses
are not delayed. However, if the CPU tries to access the SDRAM, the slave indicates that the
device is busy and the master is held by a wait signal. See
Dnd
t
RP
= 3
t
RC
= 8
AT91SAM9263 Preliminary
Figure
Row m
22-5.
t
RCD
= 3
col a
CAS = 2
Dma
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