at91sam9263 ATMEL Corporation, at91sam9263 Datasheet - Page 559

• Manufacturer Part Number: at91sam9263
• Description: At91 Arm Thumb Microcontrollers
• Manufacturer: ATMEL Corporation

34.6.1.4
34.6.2
Figure 34-8. Transmitter Block Diagram
6249D–ATARM–20-Dec-07
Transmitter Clock
Transmitter Operations
SSC_TFMR.DATLEN
Serial Clock Ratio Considerations
SSC_TCMR.STTDLY
SSC_TFMR.FSDEN
RF
Selector
Start
TF
The Transmitter and the Receiver can be programmed to operate with the clock signals provided
on either the TK or RK pins. This allows the SSC to support many slave-mode data transfers. In
this case, the maximum clock speed allowed on the RK pin is:
In addition, the maximum clock speed allowed on the TK pin is:
A transmitted frame is triggered by a start event and can be followed by synchronization data
before data transmission.
The start event is configured by setting the Transmit Clock Mode Register (SSC_TCMR).
“Start” on page 560.
The frame synchronization is configured setting the Transmit Frame Mode Register
(SSC_TFMR).
To transmit data, the transmitter uses a shift register clocked by the transmitter clock signal and
the start mode selected in the SSC_TCMR. Data is written by the application to the SSC_THR
register then transferred to the shift register according to the data format selected.
When both the SSC_THR and the transmit shift register are empty, the status flag TXEMPTY is
set in SSC_SR. When the Transmit Holding register is transferred in the Transmit shift register,
the status flag TXRDY is set in SSC_SR and additional data can be loaded in the holding
register.
– Master Clock divided by 2 if Receiver Frame Synchro is input
– Master Clock divided by 3 if Receiver Frame Synchro is output
– Master Clock divided by 6 if Transmit Frame Synchro is input
– Master Clock divided by 2 if Transmit Frame Synchro is output
SSC_TFMR.MSBF
SSC_THR
SSC_TFMR.DATDEF
See “Frame Sync” on page 562.
Transmit Shift Register
0
1
SSC_TSHR
1
0
SSC_TCMR.STTDLY
SSC_TFMR.FSDEN
SSC_TFMR.DATNB
AT91SAM9263 Preliminary
SSC_TFMR.FSLEN
SSC_CR.TXEN
SSC_CR.TXDIS
SSC_SR.TXEN
TD
See
559