at91sam9263 ATMEL Corporation, at91sam9263 Datasheet - Page 1037

• Manufacturer Part Number: at91sam9263
• Description: At91 Arm Thumb Microcontrollers
• Manufacturer: ATMEL Corporation

49.2.18
49.2.18.1
49.2.18.2
49.2.18.3
6249D–ATARM–20-Dec-07
UHP
Non-ISO IN Transfers
ISO OUT Transfers
Remote Wakeup Event
time is generally greater than the minimum safe delay required above. If not, a software wait
loop after RXSETUP clear may be added at minimum cost.
Conditions:
Consider the following scenario:
Consequence: When this error occurs, the Host controller tries the same IN token again.
Problem Fix/Workaround
This problem can be avoided if the system guarantees that the status update can be completed
within the same frame.
Conditions:
Consider the following scenario:
Consequence: After the failure condition, the Host controller stops sending the SOF. This
causes the connected device to go into suspend state.
Problem Fix/Workaround
This problem can be avoided if the system can guarantee that no buffer underrun occurs during
the transfer.
Conditions:
When a Remote Wakeup event occurs on a downstream port, the OHCI Host controller begins
to send resume signaling to the device. The Host controller should send this resume signaling
for 20 ms. However, if the driver sets the HcControl.HCFS into USBOPERATIONAL state during
the resume event, then the Host controller terminates sending the resume signal with an EOP to
the device.
1. The Host controller issues an IN token.
2. The Device provides the IN data in a short packet.
3. The Host controller writes the received data to the system memory.
4. The Host controller is now supposed to do two Write transactions (TD status write and
5. Host controller raises the request for the first write transaction. By the time the transac-
6. After completing the first write transaction, the Host controller skips the second write
1. The Host controller sends an ISO OUT token after fetching 16 bytes of data from the
2. When the Host controller is sending the ISO OUT data, because of system latencies,
3. While there is an underrun condition, if the Host controller is in the process of bit-stuff-
TD retirement write) to the system memory in order to complete the status update.
tion is completed, a frame boundary is crossed.
transaction.
system memory.
remaining bytes of the packet are not available. This results in a buffer underrun
condition.
ing, it causes the Host controller to hang.
AT91SAM9263 Preliminary
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