at91sam9263 ATMEL Corporation, at91sam9263 Datasheet - Page 486

• Manufacturer Part Number: at91sam9263
• Description: At91 Arm Thumb Microcontrollers
• Manufacturer: ATMEL Corporation

Figure 32-5. Master Write with One Data Byte
Figure 32-6. Master Write with Multiple Data Byte
Figure 32-7. Master Write with One Byte Internal Address and Multiple Data Bytes
486
TXCOMP
TXCOMP
TXRDY
TXRDY
TWD
TWD
AT91SAM9263 Preliminary
Write THR (Data n)
S
Write THR (Data n)
S
DADR
TXCOMP
DADR
TXRDY
TWD
acknowledge the byte. As with the other status bits, an interrupt can be generated if enabled in
the interrupt enable register (TWI_IER). If the slave acknowledges the byte, the data written in
the TWI_THR, is then shifted in the internal shifter and transferred. When an acknowledge is
detected, the TXRDY bit is set until a new write in the TWI_THR. When no more data is written
into the TWI_THR, the master generates a stop condition to end the transfer. The end of the
complete transfer is marked by the TWI_TXCOMP bit set to one. See
and
W
Write THR (DATA)
Figure
S
W
A
32-7.
DADR
IADR(7:0)
A
Write THR (Data n+1)
DATA n
W
A
A
DATA n
Write THR (Data n+1)
A
DATA
A
Write THR (Data n+x)
DATA n+5
Last data sent
(ACK received and TXRDY = 1)
A
STOP sent automaticaly
Write THR (Data n+x)
DATA n+5
Last data sent
P
A
DATA n+x
A
(ACK received and TXRDY = 1)
(ACK received and TXRDY = 1)
STOP sent automaticaly
Figure
DATA n+x
STOP sent automaticaly
6249D–ATARM–20-Dec-07
32-5,
A
A
Figure
P
P
32-6,