at91sam9263 ATMEL Corporation, at91sam9263 Datasheet - Page 1046

• Manufacturer Part Number: at91sam9263
• Description: At91 Arm Thumb Microcontrollers
• Manufacturer: ATMEL Corporation

49.3.12.2
49.3.13
49.3.13.1
49.3.14
49.3.14.1
49.3.14.2
49.3.14.3
49.3.14.4
1046
AT91SAM9263 Preliminary
System Controller
Two-wire Interface (TWI)
Periodic Transmission Limitations in Master Mode
Possible Event Loss when Reading RTT_SR
Clock Divider
Disabling Does Not Operate Correctly
Software Reset
STOP not Generated
If Last Significant Bit is sent first (MSBF = 0), the first TAG during the frame synchro is not sent.
Problem Fix/Workaround
None.
If an event (RTTINC or ALMS) occurs within the same slow clock cycle as when RTT_SR is
read, the corresponding bit may be cleared. This may lead to the loss of this event.
Problem Fix/Workaround
The software must handle the RTT event as an interrupt and should not poll RTT_SR.
The value of CLDIV x 2
must be less than or equal to 8191·
Problem Fix/Workaround
None.
Any transfer in progress is immediately frozen if the Control Register (TWI_CR) is written with
the bit MSDIS at 1. Furthermore, the status bits TXCOMP and TXRDY in the Status Register
(TWI_SR) are not reset.
Problem Fix/Workaround
The user must wait for the end of transfer before disabling the TWI. In addition, the interrupts
must be disabled before disabling the TWI.
When a software reset is performed during a frame and when TWCK is low, it is impossible to
initiate a new transfer in READ or WRITE mode.
Problem Fix/Workaround
None.
If the sequence described as follows occurs:
The STOP is not generated.
The line shows: DADR BYTE 1, ..., BYTE n, NO STOP generated, BYTE 1, ..., BYTE n.
1. WRITE 1 or more bytes at a given address.
2. Send a STOP.
3. Wait for TXCOMP flag.
4. READ (or WRITE) 1 or more bytes at the same address.
CKDIV
must be less than or equal to 8191, the value of CHDIV x 2
6249D–ATARM–20-Dec-07
CKDIV