at91sam9263 ATMEL Corporation, at91sam9263 Datasheet - Page 273

• Manufacturer Part Number: at91sam9263
• Description: At91 Arm Thumb Microcontrollers
• Manufacturer: ATMEL Corporation

Figure 24-2. DMAC Transfer Hierarchy for Non-Memory Peripheral
Figure 24-3. DMAC Transfer Hierarchy for Memory
6249D–ATARM–20-Dec-07
Transaction
Transfer
AMBA
Burst
Block
Burst
Block: A block of DMAC data. The amount of data (block length) is determined by the flow con-
troller. For transfers between the DMAC and memory, a block is broken directly into a sequence
of AMBA bursts and AMBA single transfers. For transfers between the DMAC and a non-mem-
ory peripheral, a block is broken into a sequence of DMAC transactions (single and bursts).
These are in turn broken into a sequence of AMBA transfers.
Transaction: A basic unit of a DMAC transfer as determined by either the hardware or software
handshaking interface. A transaction is only relevant for transfers between the DMAC and a
source or destination peripheral if the source or destination peripheral is a non-memory device.
There are two types of transactions: single and burst.
Transfer
AMBA
Burst
Block
– Single transaction: The length of a single transaction is always 1 and is converted
– Burst transaction: The length of a burst transaction is programmed into the DMAC.
Transaction
Transfer
AMBA
Burst
to a single AMBA transfer.
The burst transaction is converted into a sequence of AMBA bursts and AMBA
single transfers. DMAC executes each AMBA burst transfer by performing
incremental bursts that are no longer than the maximum AMBA burst size set. The
burst transaction length is under program control and normally bears some
Burst
Block
DMAC Transfer
Transfer
AMBA
Burst
Block
DMAC Transfer
Transaction
Transfer
AMBA
Burst
Burst
Block
Transfer
AMBA
Burst
Transfer
AMBA
Single
Block
Transfer
AMBA
Single
AT91SAM9263 Preliminary
Transaction
Transfer
AMBA
Single
Single
Block Transfer
Level
AMBA Transfer
Level
DMA Transfer
Level
Block Transfer
Level
DMA Transaction
Level
AMBA Transfer
Level
DMA Transfer
Level
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