at91sam9263 ATMEL Corporation, at91sam9263 Datasheet - Page 1052

• Manufacturer Part Number: at91sam9263
• Description: At91 Arm Thumb Microcontrollers
• Manufacturer: ATMEL Corporation

Table 50-1.
1052
Revision
6249C
AT91SAM9263 Preliminary
Revision History (Continued)
Comments
USART: In
In
reset.
CAN: In
UDP:
Updated description of bit EPEDS in the USB_CSR register on
not affected .
Updated: write
Updated: write 0 =
LCDC: In
Updated
format.
Updated bit description
configuration table with new value for 24 bpp unpacked.
In
occurences of “pin” to “signal”.
ISI: Added information to CODEC_ON bit description in
974.
Added Bit 3 CDC_PND to
Correction to name of
Added note on ISI_PCK to
Updated ISI_RST bit description in
In
Added
Updated
Corrected VDDOSC value in
Errata changes: Inserted
1028.
Inserted
Updated
Inserted
Inserted
Inserted
on page
Inserted
Section 33.6.2 “Receiver and Transmitter Control” on page
Section 43.11.24 “Power Control Register” on page
Table 46-3, “Power Consumption for Different Modes,” on page
Table 42-2 on page
Table 46-6, “Master Clock Waveform Parameters,” on page
Figure 37-7 on page 668
“EMACB”
“USART”
“SDRAM Controller”
Section 49.2.10.1 “NTRST: Device does not boot correctly due to power-up sequencing issue”
1032.
Section 49.2.3.1 “BMS Does Not Have Correct State” on page
Table 43-3, ”Little Endian Memory Organization”, on page
Section 46.5 “Crystal Oscillator Characteristics” on page
“USART”
Table 43-1, “I/O Lines Description,” on page
Section 33.5.1 “I/O Lines” on page 510
1=.....”RX_DATA_BK0: Receive Data Bank
,
,
...”TXPKTRDY: Transmit Packet Ready”
,
Section 49.2.19.1 “SCK1 and SCK2 are Inverted” on page
Section 49.2.7.1 “Transmit Underrun Errors” on page
Section 49.2.19.3 “CTS Signal in Hardware Handshake” on page
Section 45.4.8 “ISI Preview Decimation Factor Register” on page
”PIXELSIZE: Bits per pixel” on page 901
“2D Graphic Controller”
831, “Supported Endpoint” column updated in the USB Communication Flow.
Section 45.4.3 “ISI Status Register” on page
Table 45-9, “ISI Memory Mapping,” on page
Table 46-9, “32 kHz Oscillator Characteristics,” on page
,
Section 49.2.12.3 “JEDEC Standard Compatibility” on page
corrected mode switch conditions.
Section 45.4.1 “ISI Control 1 Register” on page
,
added information on TXD enabled.
Section 49.2.1.1 “Polygon Fill Function” on page
909, LCD_PWR bit description, changed all
865, updated description of LCDDEN.
Section 45.4.1 “ISI Control 1 Register” on page
0”bitfield in USB_CSR
bitfield in USB_CSR
516, corrected information on software
page 859
in LCDCON2 register, updated bit
1000ff.
995, added note for SRAM access.
998.
869, with Pixel 24 bpp unpacked
978.
973.
1028.
for details on control endpoints
1029.
1038.
974.
1000.
1038.
985.
1033.
6249D–ATARM–20-Dec-07
Change
Request
Ref.
4825
4367
4089
3476
4063
4099
3587
3518
3519
3250
3524
3904
4304
4092,
3862
4244
4093
4093
4093
4465
4221
3882