at91sam9263 ATMEL Corporation, at91sam9263 Datasheet - Page 298

• Manufacturer Part Number: at91sam9263
• Description: At91 Arm Thumb Microcontrollers
• Manufacturer: ATMEL Corporation

Figure 24-15. DMA Transfer with Linked List Source Address and Contiguous Destination Address
6249D–ATARM–20-Dec-07
Source Layer
Address of
SAR(2)
SAR(1)
SAR(0)
The DMAC transfer might look like that shown in
nation address is decrementing.
The DMA transfer flow is shown in
17. The DMAC does not wait for the block interrupt to be cleared, but continues and fetches
completion of every transaction (burst and single) in the block and carry out the block
transfer.
the next LLI from the memory location pointed to by current DMAC_LLPx register and
automatically reprograms the DMAC_SARx, DMAC_CTLx and DMAC_LLPx channel
registers. The DMAC_DARx register is left unchanged. The DMA transfer continues
until the DMAC samples the DMAC_CTLx and DMAC_LLPx registers at the end of a
block transfer match that described in Row 1 of
then knows that the previous block transferred was the last block in the DMA transfer.
Source Blocks
Block 1
Block 2
Block 0
Figure 24-16 on page
Destination Blocks
AT91SAM9263 Preliminary
Block 0
Block 2
Block 1
Figure 24-15 on page 298
Table 24-2 on page
299.
DAR(2)
DAR(0)
DAR(1)
Destination Layer
Address of
278. The DMAC
Note that the desti-
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